Patterned Buffer Layer for Stress Isolation in Stacked Dies
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Solution Overview
Problem
Stresses transmitted between stacked integrated device dies can degrade the performance of the package, and existing solutions like silicon interposers increase costs and introduce thermal mismatch issues.
Innovation Solution
A buffer layer is disposed between the integrated device die and the carrier, patterned to create gaps and protrusions that reduce stress transmission, potentially using compliant materials like polyimide or polybenzoxazole, and applied through wafer-level processing to minimize costs and improve alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon interposer is used to reduce stress transmission, then stress isolation is improved, but cost increases and thermal mismatch issues are introduced
Solution Approach 1:
The patent introduces a buffer layer as an intermediary element between the integrated device die and the carrier. This buffer layer serves as a mediator that reduces stress transmission while avoiding the thermal mismatch problems associated with silicon interposers. The buffer layer is deposited using atomic layer deposition (ALD) and can be patterned to optimize its stress isolation functionality.
Solution Approach 2:
The patent changes the material parameters and structural configuration by using a buffer layer with different mechanical properties than silicon interposers. The buffer layer's thickness, composition, and pattern geometry are optimized to achieve stress isolation. The layer can be deposited at controlled thicknesses (e.g., 1-10 micrometers) and patterned with specific gap dimensions to tune the stress transmission characteristics.
2Reliability
If a buffer layer with gaps is introduced to reduce stress transmission, then stress isolation is improved, but device complexity increases
Solution Approach 1:
The buffer layer is segmented into patterned regions with gaps, creating discrete stress isolation zones. This segmentation allows the buffer layer to effectively block stress transmission paths while maintaining a relatively simple overall structure. The gaps are strategically positioned to interrupt stress flow from the carrier to the integrated device die.
Solution Approach 2:
The patent replaces complex mechanical stress isolation structures (such as those requiring precision mechanical assembly) with a deposited buffer layer that achieves stress isolation through material properties and pattern geometry. The ALD deposition process and subsequent patterning create the stress isolation function through conformal coating and selective removal rather than complex mechanical assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buffer layer effectively reduces stress transmission between dies, improving package performance and yield by isolating sensitive components from mechanical stresses and thermal mismatches, while being more cost-effective than traditional silicon interposers.
Implementation Method 1
The buffer layer can comprise a pattern to reduce transmission of stresses between the carrier and the integrated device die
Implementation Method 2
thermal mismatches
Data Source
AI summary
An integrated device package is disclosed. The package can include a carrier, such as first integrated device die, and a second integrated device die stacked on the first integrated device die. The package can include a buffer layer which coats at least a portion of an exterior surface of the first integrated device die and which is disposed between the second integrated device die and the first integrated device die. The buffer layer can comprise a pattern to reduce transmission of stresses between the first integrated device die and the second integrated device die.