Patterned Conducting Plate Chip Package Design
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Solution Overview
Problem
Current chip packages face challenges in achieving high-speed performance while reducing fabrication cost and time, especially as demand increases for faster and smaller electronic products.
Innovation Solution
A chip package design featuring a patterned conducting plate with separated conducting sections, conducting pads, and bumps electrically connected to the plate, surrounded by an insulating support layer, which allows for efficient chip placement and reduced fabrication costs through modified etching processes and materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional chip package structure is used, then fabrication process is simpler, but signal transmission speed is slower and fabrication cost is higher
Solution Approach 1:
The conducting plate is patterned to create multiple conducting sections that are electrically separated from each other. This segmentation allows for optimized signal paths and reduced interference, enabling faster signal transmission while maintaining a relatively simple overall structure that can be fabricated using modified standard processes.
Solution Approach 2:
The insulating support layer is positioned to partially surround the conducting bumps, providing localized insulation where needed. This local quality approach optimizes electrical isolation and signal integrity without requiring complete insulation of the entire structure, balancing performance with fabrication simplicity.
2Speed
If high-speed performance is achieved through conventional means, then signal transmission improves, but fabrication time and cost increase
Solution Approach 1:
The insulating support layer is formed to partially surround the conducting bumps before final assembly steps. This preliminary action ensures proper electrical isolation is in place early in the fabrication process, preventing the need for additional post-processing steps and reducing overall fabrication time while maintaining high-speed performance.
3Productivity
If conventional chip package design is used, then structural simplicity is maintained, but fabrication cost increases and performance decreases
Solution Approach 1:
The patterned conducting plate serves multiple functions: it provides electrical connections through the conducting sections, enables signal transmission through the conducting pads, and maintains structural integrity. This multi-functionality reduces the need for separate components, improving fabrication efficiency while keeping the overall structure relatively simple.
Data Source
AI summary
A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of conducting pads disposed on an upper surface of the patterned conducting plate, wherein a recess extending from a surface of one of the conducting pads towards an inner portion of the corresponding one of the conducting pads, a chip disposed on the conducting pads, a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate, and an insulating support layer partially surrounding the conducting bumps.