Patterned Conductive Plate for HPC Warpage Control
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Solution Overview
Problem
As high-performance computing (HPC) packages grow in size, warpage control and thermal dissipation of circuit carriers become increasingly challenging, particularly in advanced networking and AI-related products that require high data rates and low latency.
Innovation Solution
A method of fabricating semiconductor devices involves using a patterned conductive plate with a specific coefficient of thermal expansion, embedded within a core dielectric material layer, which includes sub-dielectric materials and core conductive layers, to achieve effective thermal dissipation and warpage control. The patterned conductive plate is formed with apertures and laminated between sub-dielectric materials, with plated through holes providing electrical connections and build-up layers for enhanced thermal conductivity and reduced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the package size is increased to accommodate HPC components, then the computing performance and data rate are improved, but the warpage control and thermal dissipation of the circuit carrier deteriorate
Solution Approach 1:
The patent changes the physical parameters of the circuit carrier by embedding a patterned conductive plate with specific thermal conductivity and coefficient of thermal expansion. This conductive plate's parameters are optimized to counteract warpage and enhance thermal dissipation, directly resolving the contradiction between increased package size and manufacturing precision
Solution Approach 2:
The circuit carrier is designed as a composite structure combining the substrate, core dielectric material layer, and patterned conductive plate. This composite material approach allows the integration of materials with different thermal and mechanical properties to simultaneously achieve structural stability and thermal management in large-scale HPC packages
2Power
If the package size is increased to accommodate HPC components, then the computing performance and data rate are improved, but the thermal dissipation of the circuit carrier deteriorates
Solution Approach 1:
The patterned conductive plate serves as a thermal intermediary between the HPC components and the circuit carrier substrate. It conducts heat away from the high-performance components through its high thermal conductivity regions, effectively managing thermal dissipation in large-scale packages
Solution Approach 2:
The conductive plate is patterned with regions of different thermal conductivities, creating local quality variations. High thermal conductivity regions are positioned under heat-generating components for efficient heat extraction, while lower conductivity regions maintain structural integrity, solving the thermal dissipation challenge in large packages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves good thermal dissipation and warpage control by utilizing the high thermal conductivity of the patterned conductive plate and managing the coefficient of thermal expansion, resulting in improved system board performance and coplanarity.
Implementation Method 1
utilizing the high thermal conductivity of the patterned conductive plate
Implementation Method 2
managing the coefficient of thermal expansion
Data Source
AI summary
A circuit board structure includes a first core layer, a first build-up layer and a second build-up layer. The first core layer has a first surface and a second surface opposite to the first surface, wherein the first core layer includes a core dielectric material layer and at least one patterned conductive plate embedded within the core dielectric material layer, the core dielectric material layer includes a first sub-dielectric material and a second sub-dielectric material, and at least one interface exists in between the first sub-dielectric material and the second sub-dielectric material. The first build-up layer is disposed on the first surface of the first core layer, and the second build-up layer is disposed on the second surface of the first core layer.