Patterned Masking for Dielectric Fin Recessing and Bridging Control
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Solution Overview
Problem
Existing multi-gate devices, such as FinFETs and MBC transistors, face issues with dielectric fin bridging and parasitic capacitance during etching processes, leading to increased parasitic resistance and capacitance, which affect the performance of integrated circuits.
Innovation Solution
A method is introduced to form a dielectric fin between adjacent active regions and selectively etch it to a predetermined volume using a patterned masking layer with adjustable configurations, thereby controlling parasitic resistance and capacitance by adjusting the volume of the recessed dielectric fin and source/drain contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric fin is completely removed to prevent bridging, then bridging prevention is improved, but parasitic capacitance increases due to direct contact between source/drain regions
Solution Approach 1:
The patent applies local quality by creating non-uniform dielectric fin structures with different heights in different regions. The dielectric fin is selectively recessed to different depths in first and second regions, allowing the structure to simultaneously prevent bridging in critical areas while maintaining sufficient height in other areas to reduce parasitic capacitance. This localized variation in dielectric fin height optimizes both bridging prevention and parasitic capacitance reduction.
2Object-generated harmful factors
If the dielectric fin volume is reduced to reduce parasitic capacitance, then parasitic capacitance is reduced, but bridging prevention capability deteriorates
Solution Approach 1:
The patent implements local quality by differentiating the dielectric fin height across different spatial regions. The first region maintains a greater dielectric fin height for robust bridging prevention, while the second region has a reduced dielectric fin height to minimize parasitic capacitance. This spatially varying structure resolves the contradiction by optimizing each region for its specific functional requirement.
Solution Approach 2:
The patent applies segmentation by dividing the dielectric fin into distinct height zones (first region and second region). This segmentation allows independent optimization of each zone - the first zone prioritizes bridging prevention with greater height, while the second zone prioritizes parasitic capacitance reduction with lesser height, thereby resolving the overall contradiction.
3Object-generated harmful factors
If the source/drain contact area is increased to reduce parasitic resistance, then parasitic resistance is reduced, but device area increases
Solution Approach 1:
The patent utilizes the dielectric fin structure as a flexible isolation element that can be selectively recessed. By controlling the depth and pattern of dielectric fin recession, the source/drain contact area is effectively increased without proportionally increasing the overall device footprint. The thin film nature of the dielectric fin allows precise control over contact area while maintaining compact device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents dielectric fin bridging and reduces parasitic capacitance and resistance, enhancing the performance of integrated circuits by optimizing them for specific applications like high-speed communication or low-power consumption.
Implementation Method 1
etching the masking layer to adjust a volume of the dielectric fin to a predetermined amount
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes receiving a workpiece comprising a first semiconductor element and a second semiconductor element, and a dielectric fin disposed between the first semiconductor element and the second semiconductor element. The method also includes forming a masking layer directly over the dielectric fin, etching the first semiconductor element and the second semiconductor element to form a first recess and a second recess, and forming a first source/drain feature and a second source/drain feature in the first recess and the second recess, respectively. By employing a masking layer and patterning the masking layer to have different widths, a parasitic resistance and a parasitic capacitance of the semiconductor structure may be adjusted accordingly, and undesirably bridging between two adjacent epitaxial source/drain features may be prevented.