Patterned Dielectric Liner for Integrated Fan-Out Package Reliability
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving reliable and cost-effective fabrication of integrated fan-out packages due to issues with material usage and process efficiency in packaging processes, particularly in forming compact and reliable structures for integrated circuit components.
Innovation Solution
The process involves forming conductive vias and a patterned dielectric liner on a semiconductor wafer, followed by encapsulation with an insulating material, which allows for the formation of a conformal patterned dielectric liner that protects the components and reduces material usage, thereby improving reliability and yield while minimizing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If conventional packaging processes are used for integrated fan-out packages, then fabrication can proceed with standard materials and methods, but material usage is excessive and fabrication costs are high
Solution Approach 1:
The patent applies local quality by forming a patterned dielectric liner only in specific locations where conductive vias are present, rather than applying dielectric material uniformly across the entire substrate. This localized approach reduces material consumption while providing protection exactly where needed during the encapsulation process
Solution Approach 2:
The dielectric layer is segmented into a patterned configuration that corresponds to the layout of conductive vias, creating discrete protective regions rather than a continuous layer. This segmentation reduces the total amount of dielectric material required while maintaining protective functionality for each via individually
2Reliability
If conductive vias are exposed during encapsulation, then direct access to vias is achieved, but copper-bur defects occur and reliability decreases
Solution Approach 1:
The patterned dielectric liner is formed beforehand to provide a protective cushion around the conductive vias during the encapsulation process. This pre-formed protective structure prevents harmful interactions between the encapsulant material and the copper vias, eliminating copper-bur defects before they can occur
Solution Approach 2:
The patterned dielectric liner acts as an intermediary layer between the conductive vias and the encapsulant material. This intermediate structure mediates the interaction during encapsulation, preventing direct contact that would cause copper-bur defects while still allowing the encapsulation process to proceed
3Ease of manufacture
If no protective liner is used during encapsulation, then fabrication steps are simplified, but conductive vias and alignment marks are damaged
Solution Approach 1:
The patterned dielectric liner provides localized protection exactly where conductive vias and alignment marks are located, rather than requiring a complete continuous layer. This targeted approach maintains manufacturing precision for critical features while keeping the fabrication process relatively simple
Solution Approach 2:
The patterned dielectric liner is formed in advance of the encapsulation process, preparing the protective structure beforehand. This preliminary action ensures that vias and alignment marks are protected from the start of encapsulation, preventing damage without complicating subsequent fabrication steps
4Quantity of substance
If continuous dielectric layer is formed over entire substrate, then complete coverage is achieved, but material consumption increases and cost rises
Solution Approach 1:
The patterned dielectric liner implements local quality by providing dielectric coverage only in regions where conductive vias are present, rather than applying material across the entire substrate. This approach reduces dielectric material consumption while maintaining adequate protection coverage for all via locations
Solution Approach 2:
The continuous dielectric layer is segmented into discrete patterned regions that correspond to via locations. This segmentation reduces the total quantity of dielectric material required while ensuring that each via receives appropriate protective coverage through its own dedicated dielectric region
Data Source
AI summary
An integrated circuit package including an integrated circuit component, a patterned dielectric liner, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component includes an active surface and conductive vias distributed on the active surface. The patterned dielectric liner conformally covers the active surface of the integrated circuit component and sidewalls of the conductive vias. The insulating encapsulation encapsulates sidewalls of the integrated circuit component and covers the patterned dielectric liner. The insulating encapsulation includes a planar top surface. The planar top surface of the insulating encapsulation is substantially coplanar with top surfaces of the conductive vias. The insulating encapsulation and the conductive vias are spaced apart by the patterned dielectric liner. The redistribution circuit structure is disposed on the planar top surface of the insulating encapsulation, the top surfaces of the conductive vias and the patterned dielectric liner. The redistribution circuit structure is electrically connected to the conductive vias.