Patterned Epitaxial Isles for Low-Bow Semiconductor Wafers
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Solution Overview
Problem
The integration of compound semiconductor epitaxial wafers with Si-CMOS wafers faces challenges due to stress caused by the epitaxial layer, leading to wafer bow issues that are difficult to manage in standard CMOS equipment, especially when using thick Si substrates.
Innovation Solution
The method involves patterning the epitaxial layer to form epitaxial isles and dummy structures on the substrate, followed by thinning and planarization to reduce stress and achieve a standard thickness, allowing for stress-free handling and integration without wafer bow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If thick Si substrates are used to support epitaxial GaN layers, then stress compensation and bow reduction are achieved, but wafer handling difficulty and equipment compatibility issues arise
Solution Approach 1:
The epitaxial layer is patterned into discrete epitaxial isles separated by trenches, transforming the continuous stressed layer into segmented structures. This segmentation reduces the overall stress accumulation while maintaining the functional areas, allowing the wafer to be handled more easily in standard equipment without requiring excessively thick substrates for stress compensation.
Solution Approach 2:
Material is selectively removed to form trenches between the epitaxial isles. By extracting material in these trench regions, the stress distribution is modified, and the substrate thickness can be reduced while still maintaining adequate stress compensation, thereby improving wafer handling ease.
2Stability of the object's composition
If epitaxial layer is patterned into isles to reduce stress, then wafer bow is reduced, but additional processing steps are required
Solution Approach 1:
The patterning of epitaxial isles and the formation of trenches are combined into a single lithography and etching process sequence. The dielectric filling and planarization steps are merged with standard CMP processes used in CMOS fabrication, integrating the stress management features into conventional processing flows rather than adding entirely separate process modules.
3Adaptability or versatility
If substrate is thinned to standard thickness for CMOS integration, then equipment compatibility is improved, but stress-induced bow increases
Solution Approach 1:
The epitaxial layer is patterned into isles with trenches formed beforehand, before the substrate thinning process. This preliminary structuring creates a stress distribution pattern that compensates for the bow that would otherwise occur during and after thinning, allowing the substrate to be thinned to standard CMOS-compatible thicknesses without developing excessive bow.
Solution Approach 2:
The epitaxial layer is present only in specific localized regions (isles) rather than covering the entire substrate. This local quality approach concentrates the functional epitaxial material where needed while leaving trench regions without epitaxial material to act as stress relief zones, enabling thin substrate processing with minimal bow.
4Productivity
If wafer reconstitution by dicing is performed to achieve high yield, then good dies can be selected, but process complexity increases significantly
Solution Approach 1:
The epitaxial layer is pre-segmented into isles during the growth and patterning stages, creating individually addressable functional units before wafer processing. This early segmentation enables easier die separation and reconstitution operations, reducing the complexity of yield management compared to handling large continuous epitaxial wafers.
Solution Approach 2:
The patterned epitaxial isles structure acts as an intermediary that simplifies the interface between the epitaxial growth process and the subsequent wafer reconstitution process. The predefined isle geometry and spacing provide natural alignment features and stress management that facilitate automated die handling and reconstitution, reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces stress and achieves a stress-free epitaxial wafer handling process, enabling the use of epitaxial wafers in standard CMOS equipment without bow issues, enhancing integration with Si-CMOS wafers.
Implementation Method 1
the formation of the epitaxial isles by removing or etching the epitaxial layer may result in the reduction of stress caused by the epitaxial layer
Implementation Method 2
grinding or etching the substrate from the surface opposite to the plurality of epitaxial isles to the second thickness
Implementation Method 3
grinding or etching the substrate
Implementation Method 4
depositing a dielectric material on the at least one epitaxial layer to entirely cover the plurality of epitaxial isles
Implementation Method 5
polishing the dielectric material
Implementation Method 6
the additional dummy epitaxial structures, especially realized in-between the epitaxial isles, may reduce or overcome the dishing effect
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
A method (100) and a semiconductor structure are provided. The method comprises the steps of providing (101) a semiconductor structure comprising at least one epitaxial layer, and a substrate having a first thickness, removing (102) the at least one epitaxial layer from the substrate in a predefined pattern to form a plurality of epitaxial isles on the substrate, and thinning (103) the substrate from a surface opposite to the plurality of epitaxial isles to a second thickness T2.