Patterned Etch Stop Material for Reduced Interlayer Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the fabrication of advanced integrated circuits, the use of copper-based metallization layers poses challenges due to copper's tendency to diffuse in silicon dioxide and low-k dielectric materials, requiring complex processing techniques like damascene or dual damascene, which struggle with reducing parasitic capacitance and maintaining mechanical stability while ensuring reliable filling of vias with high aspect ratios and small dimensions.
Innovation Solution
The introduction of a laterally restricted etch stop material patterned into via receiving regions to control the etch process and reduce the overall dielectric constant, allowing for reliable patterning of via openings without unduly increasing parasitic capacitance, and the use of a cap material to enhance electromigration characteristics without contributing to capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous etch stop layer is used to control the etch process and provide mechanical stability, then etch control and mechanical stability are improved, but parasitic capacitance increases due to the high dielectric constant of the etch stop material
Solution Approach 1:
The continuous etch stop layer is segmented into discrete via receiving regions. The etch stop material is patterned to exist only in specific locations where vias need to be formed, rather than as a continuous layer. This segmentation maintains etch control at via locations while eliminating parasitic capacitance contribution from etch stop material in interconnect regions.
Solution Approach 2:
The etch stop material is extracted from the interconnect regions where it contributes to parasitic capacitance. Only the necessary portions for via formation are retained, removing the harmful capacitive effect while preserving the functional etch stop capability where needed.
2Object-generated harmful factors
If the dielectric constant of the interlayer dielectric material is reduced to lower parasitic capacitance, then parasitic capacitance decreases, but mechanical stability deteriorates
Solution Approach 1:
The etch stop layer is segmented into discrete via receiving regions rather than being continuous. This allows the use of low-k dielectric materials in the interconnect regions while maintaining mechanical stability through the localized presence of etch stop material in via receiving regions.
Solution Approach 2:
Different regions of the structure are assigned different material properties. The interconnect regions use low-k dielectric material for reduced parasitic capacitance, while the via receiving regions contain etch stop material for mechanical stability and etch control. Each region has the quality it needs for its specific function.
3Area of moving object
If via openings are patterned to small dimensions to reduce interconnect line dimensions, then floor space utilization improves, but etch damage and alignment inaccuracies increase
Solution Approach 1:
The via receiving regions are formed in advance as prepared zones with etch stop material before the actual via etching process. This preliminary structuring provides a defined target for via formation, improving alignment accuracy and reducing etch damage by confining the etch process to predetermined regions.
Solution Approach 2:
The via receiving regions act as intermediary structures that mediate between the photolithography patterning process and the via etching process. They provide a buffer zone that improves alignment tolerance and reduces the impact of alignment inaccuracies on the final via dimensions.
Data Source
AI summary
Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this manner, the patterning process for forming the via openings may be controlled in a highly reliable manner, while, on the other hand, the resulting overall dielectric constant of the metallization system may be reduced, thereby also significantly reducing the parasitic capacitance between stacked metal lines.