Patterned FD-SOI Wafer Fabrication With Pre-Patterned BOX Contacts
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Solution Overview
Problem
The high cost and complexity of producing patterned fully depleted silicon-on-insulator (FD-SOI) wafers due to the expensive process of patterning and etching the buried oxide layer (BOX) areas, making them unaffordable for widespread use.
Innovation Solution
A method using selective Si/SiGe wet etch chemistries and dual-use STI/Release hole patterns to create pre-patterned FD-SOI wafers from standard silicon starting substrates, which reduces the need for specialty equipment and minimizes the number of raw silicon wafers required, thereby lowering production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional methods are used to pattern FD-SOI wafers by etching the buried oxide layer, then the buried oxide layer can be exposed for body biasing, but the production cost increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-patterning the buried oxide layer during the wafer fabrication process itself, rather than performing pattern etching later. The buried oxide layer is selectively removed in specific regions before bonding, creating exposure areas that enable body biasing without requiring subsequent costly etching operations on finished wafers.
Solution Approach 2:
The patent extracts the pattern etching step from the post-fabrication process and integrates it into the initial wafer formation. By removing the buried oxide layer in predetermined patterns during manufacturing, the need for expensive specialty equipment and multiple processing steps to expose the oxide later is eliminated.
2Reliability
If the buried oxide layer is continuously formed and then patterned to expose areas for contacts, then proper electrical access is achieved, but the process complexity and additional processing steps increase
Solution Approach 1:
The patent merges the oxide patterning operation with the wafer fabrication and bonding process. Instead of separately forming a continuous buried oxide layer and then performing additional etching steps to create contact areas, the oxide is selectively removed in the desired pattern during the initial processing, combining multiple functions into a single integrated process flow.
Solution Approach 2:
The patterned exposure of the buried oxide layer is performed as a preliminary action during wafer fabrication, before bonding and subsequent device processing. This eliminates the need for complex post-bonding etching operations and reduces the overall number of process steps required.
3Reliability
If specialty equipment and multiple processing steps are used to create patterned FD-SOI wafers, then the buried oxide layer can be exposed, but the production cost and manufacturing complexity increase
Solution Approach 1:
The patent employs standard semiconductor processing equipment and techniques that are already widely available in conventional fabs, rather than requiring specialty equipment. The process uses standard photolithography, etching, and bonding tools to achieve oxide exposure, making the technology universally applicable to existing manufacturing facilities.
Solution Approach 2:
The patent uses a sacrificial layer approach where a temporary material is deposited and removed to enable oxide exposure. This sacrificial layer serves its purpose during fabrication and is then completely removed, allowing the oxide to be exposed without requiring expensive specialized equipment or complex processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the FD-SOI wafer production process, reduces costs, and allows for the creation of FD-SOI wafers with exposed buried oxide layers for substrate contacts, making them more economically viable and efficient.
Implementation Method 1
wet etching the sacrificial SiGe layer through the at least one opening in the silicon layer to partially remove SiGe material from the sacrificial SiGe layer and preserve the donor silicon layer
Implementation Method 2
depositing an SiO2 layer on the donor silicon layer
Implementation Method 3
bonding a recipient handle wafer to the etched SiO2 layer of the donor silicon wafer
Implementation Method 4
wet etching the sacrificial SiGe layer to release the donor silicon wafer from the recipient handle wafer
Data Source
AI summary
Methods for preparing a donor silicon wafer by applying a SiGe layer on a silicon substrate wafer, depositing a silicon layer on the SiGe layer, etching the silicon layer to form an opening in the silicon layer, wet etching the SiGe layer through the opening in the silicon layer to partially remove SiGe material from the SiGe layer and preserve the silicon layer, depositing a buried oxide layer on the silicon layer, etching the buried oxide layer to form a body bias area, and depositing silicon in the body bias area; bonding a recipient handle wafer to the etched buried oxide layer of the donor silicon wafer to define a BOX; and wet etching the SiGe layer to release the donor silicon wafer from the recipient handle wafer.