Patterned FET Gate Structure for Higher Channel Width Scaling

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Solution Overview

Problem

Miniaturization of semiconductor devices, such as field-effect transistors (FETs), leads to decreased drain current and operation speed due to challenges in effectively forming gate electrodes and source-drain regions on patterned semiconductor substrates, resulting in increased off-current and defects.

Innovation Solution

A semiconductor component and manufacturing method involving a patterned semiconductor substrate with raised and recessed portions, where the gate insulating film covers the surface of source-drain regions and the gate electrode is formed to fill grooves in the recessed portions, ensuring consistent impurity profiles and improved channel width, facilitating easier miniaturization and reduced off-current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor devices are miniaturized to achieve higher integration, then device density increases, but drain current amounts and operation speed decrease

Engineering Contradiction:
Improvedevice integration densityVSAvoidoperation speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The invention transitions from a planar gate structure to a three-dimensional patterned surface structure with raised and recessed portions. By forming the gate insulating film and gate electrode on this patterned surface, the effective channel width is increased in the vertical and lateral dimensions, compensating for the size reduction and maintaining drain current and operation speed despite miniaturization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The semiconductor substrate surface is locally modified with raised portions and recessed portions at specific locations. The gate insulating film thickness and gate electrode structure are locally adjusted in these patterned regions, creating areas with enhanced electrical characteristics that improve overall device performance while allowing continued miniaturization.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If the effective channel width is increased by providing gate structures on a patterned surface, then drain current improves, but alignment precision and electric field control deteriorate

Engineering Contradiction:
Improveeffective channel widthVSAvoidalignment precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patterned surface structure with raised and recessed portions is formed in advance before the gate insulating film and gate electrode are deposited. This preliminary structuring establishes precise alignment references that guide subsequent fabrication steps, ensuring that the gate structures are correctly positioned while maintaining the enhanced effective channel width.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If gate structures are formed on a patterned surface to increase effective channel width, then device performance improves, but electric field diffusion increases affecting device characteristics

Engineering Contradiction:
Improveeffective channel widthVSAvoidelectric field diffusion
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The gate insulating film structure is segmented into different thickness regions corresponding to the raised and recessed portions of the patterned surface. This segmentation creates distinct electric field zones that are better controlled and confined, preventing excessive electric field diffusion while maintaining the benefits of increased effective channel width.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240088290A1Semiconductor component and manufacturing method thereof
Publication Date: 2024.03.14 SONY GROUP CORP
  • US20240088290A1 patent drawing
  • US20240088290A1 patent drawing
  • US20240088290A1 patent drawing

AI summary

A semiconductor component including: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.