Patterned Gate Dielectric for Trench IGFET Capacitance Reduction
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Solution Overview
Problem
Trench-gated IGFET devices face high gate capacitances leading to switching losses, and existing methods to reduce these capacitances increase manufacturing costs and are not flexible enough to support multiple topographies or dielectric configurations within a single device.
Innovation Solution
A method and structure that form a semiconductor device with a patterned gate dielectric, involving the formation of trenches in a semiconductor substrate, where a thicker dielectric layer is formed along the trench surfaces and a thinner dielectric layer is formed on the sidewalls, using a photosensitive layer to selectively expose and develop the dielectric material, reducing gate capacitance while allowing for multiple gate structure configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a uniform thick dielectric layer is formed along all trench surfaces to reduce gate capacitance, then switching losses are reduced, but manufacturing complexity increases due to requiring multiple trench etch steps and spacer processes
Solution Approach 1:
The patent segments the dielectric layer into two distinct layers: a first dielectric layer formed along the lower surfaces and sidewalls of the trench, and a second dielectric layer formed along the upper surfaces. This segmentation allows each layer to have different thicknesses optimized for their specific locations, reducing gate capacitance where needed while simplifying the manufacturing process by eliminating the need for multiple etch steps and spacers.
Solution Approach 2:
The patent applies local quality by providing different dielectric thicknesses at different locations within the trench structure. The first dielectric layer provides thicker insulation along the lower surfaces and sidewalls where capacitance reduction is most beneficial, while the second dielectric layer provides appropriate coverage at the upper surfaces. This localized optimization achieves capacitance reduction without requiring complex uniform thickening processes.
2Loss of energy
If existing methods are used to thicken dielectric structures to reduce gate capacitance, then switching losses decrease, but flexibility to support multiple topographies or dielectric configurations within a single device is lost
Solution Approach 1:
The patent introduces dynamic flexibility by making the dielectric configuration adaptable to different device requirements. The method allows selective formation of the first and second dielectric layers with controllable thicknesses and coverage areas, enabling the same basic structure to support multiple topographies and dielectric configurations within a single device, thereby maintaining versatility while reducing switching losses.
Solution Approach 2:
The patent utilizes parameter changes by allowing independent control of the first and second dielectric layers' thickness, material composition, and spatial distribution. This parameter flexibility enables optimization for different device configurations and topographies without requiring a complete redesign of the dielectric structure, thus maintaining adaptability while achieving capacitance reduction.
3Reliability
If a thicker dielectric layer is formed along trench surfaces to reduce gate capacitance, then gate oxide integrity improves, but manufacturing costs increase due to additional process steps
Solution Approach 1:
The patent merges the formation of thick dielectric structures with the existing trench gate fabrication process. The first dielectric layer is formed as an integral part of the trench structure, and the second dielectric layer is subsequently formed to complete the gate structure. This merging eliminates the need for separate thickening processes and multiple etch steps, thereby improving gate oxide integrity while avoiding additional manufacturing costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach reduces gate capacitance by over 20% compared to devices with uniform dielectric layers, enabling smaller gate driver devices, reduced costs, and improved gate oxide integrity, enhancing reliability for applications like automotive and medical devices.
Implementation Method 1
using a photosensitive layer to selectively expose and develop the dielectric material
Data Source
AI summary
In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.