Patterned Ground Shield for RF Interference in 3D Stacked Semiconductors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing RF shielding methods in vertically-integrated semiconductor devices are inadequate in reducing radio-frequency coupling and interference between stacked components, as signals from one device can significantly affect neighboring devices due to their close proximity.
Innovation Solution
Incorporating a patterned ground shield (PGS) between vertically-integrated substrates, which can be formed on the surface of the topmost substrate or over the first semiconductor device, to shield RF noise and interference, utilizing metallic conductors like aluminum or copper with specific geometries and thicknesses, and electrically connecting it to a ground node for effective shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically-integrated semiconductor devices are stacked closely to increase device density, then device integration and space utilization are improved, but RF coupling and interference between neighboring devices worsen
Solution Approach 1:
A patterned ground shield (PGS) layer is introduced as an intermediary between vertically-stacked RF devices. The PGS is formed on the backside of the top substrate and selectively positioned above specific device regions that generate or are sensitive to RF signals. This intermediary structure captures and redirects RF fields to ground, preventing coupling between adjacent devices in the vertical stack while maintaining high device density.
Solution Approach 2:
The ground shield is implemented as a patterned structure rather than a continuous layer, with selective positioning above specific device regions. The PGS pattern is designed to provide shielding precisely where RF coupling problems occur, while leaving other areas open for signal transmission and device operation. This localized approach reduces interference without compromising overall device performance or requiring complete shielding of the entire substrate.
2Object-affected harmful factors
If shielding layers are added between vertically-integrated substrates to reduce RF interference, then RF coupling is reduced, but device complexity and manufacturing steps increase
Solution Approach 1:
The ground shield is segmented into a patterned structure with discrete conductive regions rather than a continuous layer. Each pattern element is strategically positioned above specific device regions requiring shielding. This segmentation provides effective RF interference reduction while minimizing the total shield material required and reducing the impact on signal transmission in non-shielded areas.
Solution Approach 2:
The shielding function is implemented by utilizing the backside of the top substrate, which is an underutilized dimension in conventional vertically-integrated devices. By forming the PGS on the backside surface and connecting it to ground through via holes, the patent adds shielding capability in a new spatial dimension without increasing the footprint or complicating the primary device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The patterned ground shield substantially reduces RF coupling and interference between neighboring devices in vertically-integrated semiconductor structures, enhancing the performance and reliability of RF semiconductor devices by predicting and strategically placing the shield to mitigate RF fields.
Implementation Method 1
a patterned ground shield (PGS) between vertically-integrated substrates, which can be formed on the surface of the topmost substrate or over the first semiconductor device, to shield RF noise and interference
Data Source
AI summary
A patterned ground shield (PGS) (130) in a vertically-integrated structure includes a patterned conductor (e.g., a metallic layer) provided between a first substrate (110) having a first semiconductor device (1120 formed therein and a second substrate (120) having a second device (122) formed therein. A bonding layer (140) is used to bond the vertically-integrated die and/or wafers. The PGS may be formed on a surface (e.g., the backside) of the second (topmost) substrate, or may be formed over the first semiconductor device—for example, on a dielectric layer formed over the first semiconductor device. The PGS may consist of parallel stripes in various patterns, or may be spiral-shaped, lattice-shaped, or the like.