Patterned Insulation Metal Substrate for Power Module Heat Dissipation
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Solution Overview
Problem
Traditional power module packages have a poor heat dissipation ability due to the stacked structure of the metal carrier, insulation layer, and conductive layer, which adversely affects their reliability.
Innovation Solution
A patterned insulation metal substrate (PIMS) is introduced, featuring a metal carrier with a patterned insulation layer partially covering it and a patterned conductive layer on top, allowing for improved heat dissipation by exposing parts of the carrier to the environment and enabling direct connection of semiconductor chips to the carrier and conductive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full-faced insulation layer is used to cover the metal carrier, then electrical insulation is improved, but heat dissipation ability deteriorates
Solution Approach 1:
The insulation layer is segmented into a patterned configuration rather than a continuous full-faced layer. This segmentation creates multiple isolated insulation regions that maintain electrical insulation where needed while leaving gaps for heat dissipation pathways to the metal carrier.
Solution Approach 2:
Different regions of the substrate are assigned different properties: areas with insulation layers provide electrical insulation, while areas without insulation layers (exposed metal carrier regions) provide thermal conduction pathways. This local differentiation resolves the contradiction between insulation and heat dissipation.
2Reliability
If a stacked structure of metal carrier, insulation layer, and conductive layer is used, then electrical insulation is improved, but heat dissipation ability deteriorates
Solution Approach 1:
The stacked structure is modified by segmenting the insulation layer into a patterned configuration, which creates thermal pathways through the metal carrier while maintaining electrical insulation in specific regions. The conductive layer is also patterned to establish electrical connections without requiring continuous insulation.
Solution Approach 2:
portions of the insulation layer are extracted or removed to create exposed metal carrier regions. This extraction eliminates the thermal barrier in those specific areas, allowing heat to dissipate directly through the metal carrier while insulation is retained in other areas for electrical protection.
3Ease of manufacture
If a full-faced insulation layer is used, then manufacturing simplicity is maintained, but heat dissipation ability deteriorates
Solution Approach 1:
The insulation layer is formed with a patterned configuration using standard photolithography and etching processes. This segmentation is achieved through conventional manufacturing techniques, maintaining ease of manufacture while improving heat dissipation through the exposed metal carrier regions.
Solution Approach 2:
The pattern design parameters (insulation layer thickness, pattern geometry, spacing) are optimized to balance manufacturing simplicity with heat dissipation performance. By adjusting these parameters, the structure achieves improved thermal management using existing manufacturing capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances heat dissipation and reliability of power module packages by allowing heat generated from semiconductor chips to be effectively dissipated through the metal carrier, improving their performance compared to traditional packages.
Implementation Method 1
heat generated from semiconductor chips to be effectively dissipated through the metal carrier
Data Source
AI summary
A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.