Patterned Metal Foil Semiconductor Package for Thin Profile
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Solution Overview
Problem
Current semiconductor packaging methods result in increased thickness and manufacturing costs due to the use of bulky materials, which hinders the miniaturization of semiconductor packages and affects the yield of the wire-bonding process.
Innovation Solution
A semiconductor package design utilizing a patterned metal foil with a dielectric layer that forms a thin carrying board, allowing for secure chip placement without increasing the package thickness, and includes a patterned dielectric layer with openings for external electrical connections and a molding compound to cover the chip and wires, thereby reducing thickness and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bulky materials are used in semiconductor packaging, then the chip is well protected and electrical connections are established, but the package thickness increases and manufacturing costs increase
Solution Approach 1:
The patent uses a thin metal foil as the carrier substrate instead of bulky traditional packaging materials. This metal foil provides mechanical support and electrical connectivity while maintaining a thin profile, directly addressing the contradiction between protection and thickness.
Solution Approach 2:
The patent employs a composite structure consisting of a metal foil carrier with patterned dielectric layers and conductive patterns. This composite material approach provides both mechanical protection and electrical functionality in a thin, integrated structure that reduces overall package thickness while maintaining reliability.
2Reliability
If bulky materials are used in semiconductor packaging, then the chip is well protected, but manufacturing costs increase
Solution Approach 1:
The patent combines multiple functions into the metal foil carrier itself - it serves as the substrate, electrical interconnect, and mechanical support structure. This merging eliminates the need for separate bulky packaging components, reducing both material costs and manufacturing complexity while maintaining chip protection.
Solution Approach 2:
The patent changes the physical parameters of the packaging materials by using thin metal foil instead of bulky traditional materials. This parameter change (reducing thickness and density) directly reduces material costs and manufacturing complexity while maintaining adequate protection through the engineered composite structure.
3Reliability
If traditional packaging materials are used, then the chip is protected, but the package cannot be miniaturized
Solution Approach 1:
The thin metal foil carrier enables package miniaturization by providing adequate mechanical support and protection in a thin profile. This allows the overall package volume to be reduced while maintaining chip protection through the engineered composite structure.
Solution Approach 2:
The composite material structure of thin metal foil with patterned dielectric and conductive layers provides high functionality in a compact form factor, enabling package miniaturization while maintaining adequate chip protection.
4Reliability
If wire-bonding is performed on bulky materials, then electrical connections are established, but the bonding yield is affected
Solution Approach 1:
The patent applies local quality by creating patterned conductive regions and openings in the dielectric layer at specific locations where wire bonds need to be made. This localized structuring provides optimal bonding surfaces and pathways, improving wire-bonding yield compared to uniform bulky materials.
Solution Approach 2:
The patent changes the physical parameters of the bonding interface by using thin metal foil with controlled surface properties, whereas traditional bulky materials have less controlled interfaces. This parameter change improves wire-bonding yield by providing more consistent bonding surfaces and better heat dissipation during the bonding process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a thin, cost-effective semiconductor package that maintains secure chip placement and improves wire-bonding yield by using a patterned metal foil and dielectric layer combination, allowing for efficient heat dissipation and electrical connectivity without increasing the package thickness.
Implementation Method 1
an adhesive layer, disposed between the chip and the patterned metal foil
Implementation Method 2
a plurality of wires, respectively connecting the chip and the patterned metal foil
Implementation Method 3
a molding compound, disposed on the first surface and covering the chip and the wires
Implementation Method 4
dissipating heat generated by the chip to external surroundings
Data Source
AI summary
A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.