Patterned Metal Pad with Embedded Dielectrics for TSV Interposers
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing three-dimensional integrated circuits (3D ICs) due to physical limits in two-dimensional integration density and complex designs required for increased component integration, which are addressed by developing new packaging technologies that utilize through silicon vias (TSVs) and through-package-vias (TPVs) for electrical connections and heat dissipation.
Innovation Solution
The solution involves a package structure with a die bonded to an interposer, which is further bonded to a substrate, using TSVs and TPVs for electrical connections and heat dissipation, along with a patterned metal pad embedded with dielectric structures to reduce dishing effects and improve yield by ensuring multiple TSV connections to the pad and UBM structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional two-dimensional integration is used to increase component integration density, then more components can be integrated into a given area, but physical limits are reached and package area increases
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking multiple semiconductor dies and interposers vertically. Through-silicon vias (TSVs) enable electrical connections through the vertical stack, allowing high-density integration without increasing package footprint area.
2Manufacturing precision
If sequential metal deposition and lithography are used to form circuit components, then precise patterning is achieved, but manufacturing complexity and process steps increase
Solution Approach 1:
The manufacturing process is segmented into modular stages: forming TSVs in interposer, bonding first die, forming TSVs in first die, bonding second die, and forming final metal pads. Each stage is independently optimized, reducing overall process complexity while maintaining precision.
Solution Approach 2:
TSVs are formed in the interposer and dies before final die bonding and metal pad formation. This preliminary formation of conductive vias enables subsequent simplified metal deposition and reduces the complexity of final patterning operations.
3Ease of manufacture
If metal pads are formed over TSVs without dielectric structures, then simple fabrication is maintained, but dishing effects occur and yield decreases
Solution Approach 1:
Dielectric structures are selectively embedded only in specific regions of the metal pad that are not over TSVs. This local modification provides dishing compensation where needed while maintaining simple fabrication elsewhere, and ensures TSV connections remain unaffected.
Solution Approach 2:
Dielectric structures serve as intermediary elements between the metal pad and substrate in regions not over TSVs. These structures compensate for dishing effects during CMP processing, improving metal pad uniformity without complicating the overall fabrication process.
4Device complexity
If single TSV connection to metal pad is used, then simple structure is maintained, but reliability and fault tolerance decrease
Solution Approach 1:
The design parameters of the metal pad are optimized to accommodate multiple TSV connections, including pad size, shape, and positioning. This enables redundant electrical pathways while maintaining a relatively simple overall structure, improving reliability without excessive complexity.
Data Source
AI summary
Various embodiments of mechanisms for forming through a three-dimensional integrated circuit (3DIC) structure are provided. The 3DIC structure includes an interposer bonded to a die and a substrate. The interposer has a conductive structure with through silicon vias (TSVs) connected to a patterned metal pad and a conductive structure on opposite ends of the TSVs. The pattern metal pad is embedded with dielectric structures to reduce dishing effect and has regions over TSVs that are free of the dielectric structures. The conductive structure has 2 or more TSVs. By using a patterned metal pad and 2 or more TSVs, the reliability and yield of the conductive structure and the 3DIC structure are improved.


