Patterned Metal Sheet Roughness for Lower Thermal Resistance Packaging

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Solution Overview

Problem

Semiconductor packages face increased thermal resistance due to uneven electrolytic layers formed during soldering, which can hinder efficient heat dissipation from the semiconductor chip to the heat sink.

Innovation Solution

A metal sheet with a pattern of first subdivisions having a higher average roughness and second subdivisions with a lower average roughness is used, which directs the electrolytic layer to accumulate primarily over the smoother areas, minimizing unevenness and reducing thermal resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If electrolytic layers are applied during soldering, then the semiconductor package can be soldered to a circuit board, but unevennesses arise in the electrolytic layers which enlarge the heat conducting path and increase thermal resistance

Engineering Contradiction:
Improvesoldering capabilityVSAvoiduniformity of electrolytic layer
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The metal sheet is divided into different regions with different surface roughness characteristics. First subdivisions have a first average roughness while second subdivisions have a second average roughness that is lower than the first. This local variation in surface quality directs the electrolytic layer to accumulate primarily over the smoother second subdivisions, minimizing unevenness in the solderable areas while maintaining soldering capability.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If electrolytic layers are applied during soldering, then the semiconductor package can be soldered to a circuit board, but the heat conducting path between semiconductor chip and heat sink is enlarged, increasing thermal resistance

Engineering Contradiction:
Improvesoldering capabilityVSAvoidheat dissipation efficiency
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The metal sheet is divided into different regions with different surface roughness characteristics. First subdivisions have a first average roughness while second subdivisions have a second average roughness that is lower than the first. This local variation in surface quality directs the electrolytic layer to accumulate primarily over the smoother second subdivisions, minimizing unevenness in the solderable areas while maintaining soldering capability.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If the first sheet surface has a pattern with varying roughness, then the electrolytic layer unevenness is minimized and thermal resistance is reduced, but the manufacturing process becomes more complex

Engineering Contradiction:
Improveuniformity of electrolytic layerVSAvoidcomplexity of metal sheet pattern
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The surface roughness parameter of the metal sheet is intentionally varied across different regions. First subdivisions have a first average roughness while second subdivisions have a second average roughness that is lower than the first. This controlled variation in the roughness parameter creates predictable accumulation behavior for the electrolytic layer, minimizing unevenness while the pattern can be produced using standard manufacturing techniques.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The pattern effectively reduces the maximum depth of unevenness in the electrolytic layer, enhancing heat dissipation by minimizing thermal resistance between the semiconductor chip and the heat sink, while maintaining a more cost-effective and straightforward production process.

Implementation Method 1

During the soldering process, for example, unevennesses can arise in such electrolytic layers and they enlarge the heat conducting path between semiconductor chip and heat sink

Methodology Applied
Scientific EffectElectrolytic deposition: Electrodeposition

Data Source

PatentUS11901257B2Semiconductor package, metal sheet for use in a semiconductor package, and method for producing a semiconductor package
Publication Date: 2024.02.13 INFINEON TECHNOLOGIES AG
  • US11901257B2 patent drawing
  • US11901257B2 patent drawing
  • US11901257B2 patent drawing

AI summary

A semiconductor package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and a metal sheet having a first sheet surface and an opposite second sheet surface. The first sheet surface is exposed at the encapsulation body. The semiconductor chip is arranged at the second sheet surface. The first sheet surface has a pattern having first subdivisions having a first average roughness and second subdivisions having a second average roughness. The first average roughness is greater than the second average roughness.