Patterned Passivation Layer for Oxide TFT Stability
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Solution Overview
Problem
Oxide semiconductor thin film transistors (TFTs) are prone to instability due to external moisture and hydrogen ion diffusion, leading to threshold voltage shifts and capacitive coupling issues, and existing passivation methods either introduce hydrogen ions or have low sputtering rates, resulting in etching undercut and yield reduction.
Innovation Solution
A thin film transistor structure featuring a first patterned passivation layer with a metal oxide, ranging from 50 to 300 angstroms in thickness, and a second patterned passivation layer covering the first layer, substrate, and metal layers, which prevents hydrogen ion diffusion and external moisture ingress, while reducing capacitive coupling and fabrication time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PECVD process is used to form passivation layer, then manufacturing efficiency is improved, but hydrogen ions diffuse into oxide semiconductor causing threshold voltage shift
Solution Approach 1:
The patent extracts and removes the harmful hydrogen ions from the system by avoiding PECVD processes that introduce hydrogen, instead using PVD methods that form hydrogen-free passivation layers, thus preventing threshold voltage shift while maintaining manufacturing efficiency
Solution Approach 2:
The patent creates an inert environment by using physical vapor deposition (PVD) processes that do not introduce hydrogen ions, forming a hydrogen-free passivation layer that protects the oxide semiconductor from hydrogen diffusion while maintaining production efficiency
2Reliability
If PVD process is used to form non-hydrogen passivation layer, then threshold voltage stability is improved, but sputtering rate is low causing increased fabrication time
Solution Approach 1:
The patent merges multiple functions into a single optimized PVD passivation layer that provides both hydrogen barrier protection and high-speed deposition, combining the advantages of hydrogen-free environment with improved sputtering rates to reduce fabrication time
Solution Approach 2:
The patent changes the parameters of the PVD process to optimize the sputtering rate, adjusting power, pressure, and material composition to achieve both high deposition speed and effective hydrogen barrier properties, thereby reducing fabrication time while maintaining threshold voltage stability
3Reliability
If thick passivation layer is formed to prevent moisture ingress, then device stability is improved, but etching undercut occurs and pixel electrode formation becomes discontinuous
Solution Approach 1:
The patent uses composite material structures with optimized passivation layer composition that provides effective moisture barrier properties at reduced thickness, preventing etching undercut while maintaining device stability and ensuring continuous pixel electrode formation
Solution Approach 2:
The patent changes the material composition and physical parameters of the passivation layer to achieve optimal thickness reduction, modifying refractive index, etch selectivity, and barrier properties to prevent moisture ingress without causing etching undercut, thus maintaining pixel electrode continuity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-layer passivation structure enhances the stability and reliability of the TFT by preventing hydrogen ion diffusion and external moisture ingress, reducing capacitive coupling effects, and shortening fabrication time, making it suitable for mass production.
Implementation Method 1
the first and the second patterned passivation layers which are non-hydrogen films avoid hydrogen ions diffusing into the channel layer
Implementation Method 2
the combination of the first and the second patterned passivation layers prevent external moisture from entering the channel layer
Data Source
AI summary
A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a gate insulating layer, a source and a drain, a channel layer, and first and second patterned passivation layers. The gate is disposed on the substrate. The gate insulating layer is disposed on the gate. The source and the drain are disposed on the gate insulating layer. The channel layer is disposed above or under the source and the drain, wherein a portion of the channel layer is exposed between the source and the drain. The first patterned passivation layer is disposed on the portion of the channel layer, wherein the first patterned passivation layer includes metal oxide, and the first patterned passivation layer has a thickness ranging from 50 angstroms to 300 angstroms. The second patterned passivation layer covers the first patterned passivation layer, the gate insulating layer, and the source and the drain.