Patterned Resin Layer Warpage Control in IC Packaging
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Solution Overview
Problem
Current multi-chip and multi-package packaging technologies face significant challenges in controlling warpage, particularly in Package-on-Package (PoP) technology, due to coefficient of thermal expansion (CTE) mismatch between semiconductor chips and substrates, leading to difficulties in meeting stringent warpage specifications.
Innovation Solution
A patterned resin layer is applied over the substrate to substantially remove warpage by adjusting its coefficient of thermal expansion (CTE), filler loading, curing shrinkage factor, thickness, and area of coverage, inducing a 'reverse' warpage that offsets the original warpage, ensuring a flat package configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-chip and multi-package packaging technologies are used to increase integrated circuit density, then packaging density and performance are improved, but warpage control becomes difficult due to CTE mismatch between semiconductor chips and substrates
Solution Approach 1:
The patent changes the physical-chemical parameters of the substrate by incorporating a patterned low-expansion material layer with specific CTE values (0-7 ppm/°C) and controlled thickness (1-10 micrometers) to counteract the warpage caused by CTE mismatch during thermal cycling
Solution Approach 2:
The patent creates a composite substrate structure combining a base substrate with a patterned low-expansion material layer, where the composite structure's overall CTE is engineered to match the semiconductor chip, reducing warpage while maintaining high packaging density
2Volume of moving object
If Package-on-Package (PoP) technology with flip chip interconnection is employed, then integrated circuit density and miniaturization are achieved, but base package warpage becomes a significant limitation making it unfeasible to meet warpage specifications
Solution Approach 1:
The patent applies local quality by using a patterned low-expansion material layer with specific geometric patterns (such as grid patterns with 50-200 micrometer spacing) that locally compensate for warpage stress in critical areas while maintaining overall package miniaturization
3Shape
If strict warpage specification is imposed to achieve flatness, then package flatness is improved, but it becomes difficult to meet specifications due to CTE mismatch between chip and substrate
Solution Approach 1:
The patent applies preliminary action by pre-compensating for warpage through the patterned low-expansion material layer design before the warpage actually occurs during thermal cycling, allowing the package to meet flatness specifications while maintaining reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively neutralizes warpage, facilitates compliance with strict warpage specifications, improves reliability, and enhances packaging density and performance, while reducing manufacturing complexity and costs.
Implementation Method 1
a negative curvature ('crying' warpage) results after the chip attach and the underfill processes are completed. This is expected due to the coefficient of thermal expansion (CTE) mismatch between semiconductor chip and the substrate
Implementation Method 2
adjusting its coefficient of thermal expansion (CTE), filler loading, curing shrinkage factor, thickness, and area of coverage, inducing a 'reverse' warpage that offsets the original warpage
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system is provided including: providing a substrate; placing a patterned layer over the substrate for substantially removing crying warpage from the substrate, the patterned layer having an opening surrounded by other openings with the substrate exposed from the patterned layer within the other openings; mounting a semiconductor chip within the opening; and attaching a component directly over the other openings, the component having a horizontal length greater than horizontal lengths of the other openings.