Patterned Semiconductor Bases via Spacer Patterning
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Solution Overview
Problem
Current photolithographic techniques face limitations in reducing feature size due to minimum pitch constraints, making it challenging to achieve different levels of pitch multiplication across various regions of a semiconductor substrate without introducing complexity into the fabrication process.
Innovation Solution
A method involving the formation of patterns with different pitches on a semiconductor base using a stack of materials, where lateral trimming and spacer formation enable the transfer of patterns into underlying materials, allowing for efficient formation of high-density structures and peripheral circuitry with varying pitches through common process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic techniques are used to reduce feature size, then manufacturing precision is improved, but the minimum pitch constraint prevents further reduction
Solution Approach 1:
The patent divides the semiconductor substrate into multiple regions, each receiving different pitch multiplication treatments. Some regions undergo pitch doubling while others undergo pitch quadrupling, allowing different feature sizes to be achieved in different areas using the same photolithographic process
Solution Approach 2:
The patent introduces a spatial dimension by creating regional variations in pitch multiplication across the substrate. Instead of uniform pitch reduction, the process applies different multiplication factors to different spatial regions, enabling both high-density memory arrays and peripheral circuitry to be fabricated simultaneously
2Adaptability or versatility
If different levels of pitch multiplication are applied across different regions, then adaptability is improved, but process complexity increases
Solution Approach 1:
The patent employs a universal set of process steps that serves multiple functions: the same spacer formation, lateral trimming, and pattern transfer processes achieve both pitch doubling and pitch quadrupling depending on the region. This multi-functionality reduces the need for separate process lines for different pitch requirements
Solution Approach 2:
The patent performs preliminary patterning actions that prepare the substrate for subsequent pitch multiplication. Mask patterns are formed in advance with specific geometries that enable different multiplication factors in different regions, and spacer materials are deposited beforehand to define the final feature dimensions
Data Source
AI summary
Some embodiments include patterning methods. First and second masking features may be formed over first and second regions of a semiconductor base, respectively. A protective mask may be formed over the second masking features. First and second spacers may be formed along sidewall edges of the first masking features and along lateral edges of the protective mask, respectively. The protective mask and the first masking features may be removed without removing the second masking features, without removing the first spacers, and without removing the second spacers. The first spacers may be third masking features that are at a tighter pitch than the first masking features. Patterns of the second masking features and the third masking features may be transferred into the semiconductor base. Some embodiments include patterned semiconductor bases.