Patterned Spacer Block for Dual-Side Cooled Power Module
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Solution Overview
Problem
High power semiconductor devices face thermal management challenges due to coefficient of thermal expansion (CTE) mismatches between components in dual-side cooled packages, leading to stress-induced die crack formation, solder voids, and reliability issues.
Innovation Solution
The implementation of a spacer block with patterned surface regions featuring pillars and grooves, or cavities, and a grooved substrate design to reduce CTE mismatches by modifying heat flow paths and contact areas between the device die and the spacer block, thereby mitigating thermal gradients and inhomogeneities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a dual-side cooled package structure is used for high power semiconductor devices, then thermal management performance is improved, but coefficient of thermal expansion (CTE) mismatches between components cause stress-induced die crack formation and solder voids
Solution Approach 1:
The spacer block is designed with non-uniform geometry, featuring a first region with a first geometry and a second region with a second geometry. This local variation in geometry allows different regions of the spacer block to have different effective CTE values, enabling tailored stress management in specific areas while maintaining overall thermal management performance.
Solution Approach 2:
The invention changes the geometric parameters of the spacer block to modify its thermal expansion characteristics. By adjusting the geometry (such as thickness, width, or shape) of different regions, the effective CTE of the spacer block is altered to better match the CTE of adjacent components like the substrate and device, thereby reducing thermal stress.
2Strength
If CTE mismatches between DBM substrate, spacer block and device die are reduced through patterned surfaces and cavities, then mechanical integrity is improved, but heat transfer efficiency may be compromised
Solution Approach 1:
The spacer block incorporates localized features such as cavities in a first region and patterned surfaces in a second region. These local modifications are strategically placed to reduce CTE mismatch stress in specific areas while minimizing interference with heat transfer pathways. The patterned surfaces and cavities are designed to maintain adequate thermal conduction while accommodating differential thermal expansion.
Solution Approach 2:
The spacer block can be constructed from composite materials or materials with graded properties that combine the benefits of low CTE mismatch and high thermal conductivity. By selecting materials with appropriate thermal and mechanical properties, the spacer block achieves both mechanical integrity and heat transfer efficiency simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces thermal stress and improves the mechanical and structural integrity of the device package, enhancing reliability and thermal management while maintaining adequate heat transfer for cooling.
Implementation Method 1
modifying heat flow paths and contact areas between the device die and the spacer block, thereby mitigating thermal gradients and inhomogeneities
Implementation Method 2
at least partially reducing coefficient of thermal expansion (CTE) mismatches between the DBM substrate, the spacer block and the device die
Data Source
AI summary
A method includes bonding a device die to a direct bonded metal (DBM) substrate, bonding a spacer block to the device die, and at least partially reducing coefficient of thermal expansion (CTE) mismatches between the DBM substrate, the spacer block and the device die. At least partially reducing the CTE mismatches between the DBM substrate, the spacer block and the device die includes at least one of: disposing an arrangement of pillars and grooves in a surface region of the spacer block coupled to the device die, disposing at least one cavity in the spacer block, and disposing a groove in an outer conductive layer of the DBM substrate.