Patterned Conductive Substrate Layout for Low-Inductance Power Modules
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Solution Overview
Problem
Parasitic inductances in semiconductor device packages limit the switching speed of power modules due to increased transient voltages, particularly in high-speed devices like GaN or SiC, as the increased switching speed results in higher current changes over time.
Innovation Solution
A semiconductor device with a patterned conductive substrate featuring electrically isolated conductive regions, where switches and passive components are strategically arranged to minimize parasitic inductance, using a direct bonded copper substrate for enhanced thermal performance and reduced inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed power switching devices (GaN or SiC) are used to increase switching speed, then the switching speed is improved, but the transient voltage increases due to higher di/dt and parasitic inductance
Solution Approach 1:
The conductive layer is segmented into multiple electrically isolated conductive regions (first, second, third, and fourth conductive regions) that are spatially distributed and electrically independent. This segmentation allows for optimized current paths and reduced loop inductance by placing switching devices and passive components on different isolated regions, thereby mitigating transient voltage effects while maintaining high switching speed.
Solution Approach 2:
The patent transitions from a conventional two-dimensional PCB layout to a three-dimensional stacked architecture where switching devices and passive components are vertically integrated on different layers. The conductive regions are distributed across multiple layers with vertical interconnections, creating compact current loops that reduce parasitic inductance and allow high-speed switching without excessive transient voltage.
2Ease of manufacture
If traditional package designs are used, then manufacturing is simpler, but parasitic inductance limits switching speed and thermal performance
Solution Approach 1:
The conductive layer serves multiple functions simultaneously: it provides electrical interconnection between components, acts as a thermal management pathway, and enables compact three-dimensional integration. The insulating layer with embedded conductive regions functions as both a substrate and an interconnect structure, reducing the need for separate wiring layers and simplifying manufacturing while achieving low inductance and high switching speed.
3Object-affected harmful factors
If components are closely integrated to reduce inductance, then parasitic inductance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the substrate function with the interconnect function by embedding conductive regions directly within the insulating layer. This integration eliminates the need for separate wiring layers and reduces the number of assembly steps. The conductive regions are formed as part of the substrate structure itself, which relaxes alignment requirements compared to multi-layer PCB stacking while achieving compact current loops and low parasitic inductance.
Data Source
AI summary
One example includes an apparatus that includes an insulating layer and an electrically conductive layer on the insulating layer. The conductive layer includes a plurality of electrically isolated and conductive regions. A first switch is on a first of the conductive regions, and the first switch has a first terminal and a second terminal. A second switch is on a second of the conductive regions, and the second switch has a third terminal and fourth terminal. A passive component has a fifth terminal and a sixth terminal. The first and third terminals are coupled to the first conductive region. The fourth and sixth terminals are coupled to the second conductive region. The second and fifth terminals are coupled to a third of the conductive regions.