Patterned Substrate for Group III Nitride Epitaxy

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Solution Overview

Problem

Existing semiconductor technologies face challenges in minimizing dislocation density in semiconductor layers, particularly for light emitting devices like LEDs, especially deep ultraviolet LEDs, which affects efficiency, and current methods for patterned substrates have limitations in stress reduction and dislocation control.

Innovation Solution

A method involving a patterned substrate with a substantially flat top surface and stress-reducing regions, such as openings, is used to grow group III nitride-based semiconductor layers with high aluminum concentration, where the surface roughness is maintained below 0.5 nanometers and the openings have specific sizes and depths to facilitate stress reduction and dislocation minimization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional substrate patterning methods are used to reduce dislocation density, then dislocation control improves, but stress reduction and manufacturing precision are compromised

Engineering Contradiction:
Improvedislocation density controlVSAvoidsurface flatness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The substrate surface is segmented into multiple regions with different depths (first depth for openings, second depth for recesses), allowing independent optimization of stress reduction (via openings) and dislocation control (via recesses) without compromising overall surface flatness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the substrate surface are given different local properties: openings provide stress reduction, while recesses provide dislocation accumulation zones. The surface maintains overall flatness through precise control of these localized features

Inventive Principle:
Principle #3Local quality

2Stress or pressure

If openings are introduced into the substrate to reduce stress, then stress management improves, but dislocation density control deteriorates

Engineering Contradiction:
Improvestress reductionVSAvoiddislocation density
Core Design Contradiction:
Stress or pressureVSReliability

Solution Approach 1:

The stress management function is separated from dislocation control by creating distinct structural features: openings for stress relief and recesses for dislocation management, allowing both functions to operate independently and effectively

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The recesses act as intermediary structures between the openings and the semiconductor layer, providing a controlled environment that manages dislocations while allowing the openings to perform their stress reduction function

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If the semiconductor layer thickness is increased to achieve desired device performance, then device efficiency improves, but stress accumulation and dislocation propagation worsen

Engineering Contradiction:
Improvedevice efficiencyVSAvoidstress and dislocation management
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Stress reduction features (openings) and dislocation control features (recesses) are prepared in advance in the substrate before growing the semiconductor layer, allowing the layer to be grown to the required thickness without accumulating excessive stress or dislocations

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces dislocation density and stress in semiconductor layers, enhancing the efficiency and performance of light emitting devices by promoting epitaxial growth with reduced dislocations and improved stress management.

Implementation Method 1

growing a second layer directly on the top surface of the first layer, wherein the second layer is formed of a group III-nitride material

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS10622515B2Patterned layer design for group III nitride layer growth
Publication Date: 2020.04.14 SENSOR ELECTRONIC TECHNOLOGY INC
  • US10622515B2 patent drawing
  • US10622515B2 patent drawing
  • US10622515B2 patent drawing

AI summary

A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.