Patterned Thermoconductive Layer for III-Nitride Devices
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Solution Overview
Problem
The large lattice and thermal expansion mismatch between high thermal conductivity substrates and III-Nitride materials leads to strain issues, making it difficult to manufacture large wafer size III-Nitride semiconductor devices on high thermal conductive substrates due to wafer bow and cracking.
Innovation Solution
A method involving the formation of a patterned thermoconductive layer with high thermal conductivity, such as diamond, aligned with a patterned dielectric layer, and a back barrier layer of Group III-Nitride material, which reduces strain by using a micronized grind or diamond seedling layer to control diamond growth, allowing for the formation of a hatched patterned thermal conductive layer that matches the heat-generating device positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a high thermal conductivity substrate (diamond) is bonded to the entire III-Nitride device structure, then thermal conductivity is improved, but lattice and thermal expansion mismatch causes large strain leading to wafer bow and cracking
Solution Approach 1:
The patent segments the thermal conduction function by introducing a patterned thermoconductive layer that covers only specific heat-generating regions rather than the entire wafer. This localized approach reduces the overall strain while maintaining thermal management where needed most.
Solution Approach 2:
The patent applies local quality by making the thermal conductivity distribution non-uniform across the wafer surface. The patterned thermoconductive layer provides high thermal conductivity only in regions where heat generation occurs, while other regions maintain lower strain levels.
2Productivity
If the wafer size is increased to improve productivity, then manufacturing efficiency is improved, but strain from lattice mismatch increases causing wafer bow and cracking
Solution Approach 1:
The patterned thermoconductive layer segments the strain distribution across the wafer, allowing larger wafer sizes to be used without uniform strain across the entire surface. This enables increased productivity while maintaining wafer integrity.
3Ease of manufacture
If a complete back barrier layer is removed to simplify manufacturing, then process complexity is reduced, but device performance deteriorates due to loss of strain management functionality
Solution Approach 1:
The patent extracts only the necessary portion of the back barrier layer in the patterned regions, removing material where it is not needed while preserving it in regions where it provides strain management functionality. This reduces process complexity while maintaining device performance.
Solution Approach 2:
The patent applies local quality by having different back barrier layer configurations in different regions - removed or thinned in some areas, preserved in others - based on the specific strain management needs of each region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces strain and enables the manufacture of large wafer size III-Nitride semiconductor devices on high thermal conductive substrates by minimizing wafer bow and preventing cracking, thereby improving the manufacturability of these devices.
Implementation Method 1
uses a diamond seedling layer as the high thermal conductive seedling layer and controls the diamond growth conditions so that a diamond layer only glows on the diamond seedling layer and a patterned thermal conductive layer formed of diamond is formed
Implementation Method 2
forms a patterned thermoconductive layer on the patterned dielectric layer... The pattern of the thermoconductive layer is the same as the pattern of the patterned dielectric layer... the patterned thermoconductive layer has a thermal conductivity of at least 500 W/(m-k)
Data Source
AI summary
The present disclosure includes but is not limited to the III-Nitride semiconductor devices including a barrier layer, a gallium nitride or indium gallium nitride channel layer having a Ga-face coupled with the barrier layer, and a patterned thermoconductive layer having a thermal conductivity of at least 500 W/(m-K) within 1000 nanometers of a Ga-face of the gallium nitride channel layer. The semiconductor device may be a high-electron-mobility transistor or a semiconductor wafer. Methods for making the same also are described.