Patterning Device Pattern Optimization for Sub-k1 Lithography
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Solution Overview
Problem
Current lithography methods face challenges in optimizing patterning device patterns to effectively connect and process closely adjacent polygons, leading to inefficiencies in printing sub-k1 limit features, which requires multiple exposures and complex optimization processes.
Innovation Solution
A method that involves identifying and connecting closely adjacent polygons, applying evaluation features outside their boundaries, and generating a guide contour to create a patterning device pattern that spans across these connected polygons, optimizing the illumination mode and pattern to achieve accurate edge placement and reduce the need for multiple exposures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple exposures are used to print sub-k1 limit features, then the patterning capability is improved, but the manufacturing complexity and process time increase
Solution Approach 1:
The patent combines multiple patterning operations into a single exposure by merging closely adjacent polygons into connected components. The guide contour spans across these connected polygons, allowing the lithography apparatus to print sub-k1 limit features in one go rather than requiring multiple sequential exposures, thus reducing manufacturing complexity while maintaining patterning precision.
Solution Approach 2:
The patent performs preliminary processing of the design pattern by identifying and connecting closely adjacent polygons before the actual lithography exposure. Evaluation features are placed and guide contours are generated in advance, preparing the pattern data structure to enable single-exposure printing of sub-k1 features, thereby avoiding the need for multiple subsequent exposures.
2Manufacturing precision
If multiple patterning processes are used, then the pattern fidelity is improved, but the production time and cost increase
Solution Approach 1:
The patent merges multiple patterning processes into a single lithography step by creating connected components from closely adjacent polygons and generating guide contours that span across these connections. This allows the pattern to be printed with high fidelity in one exposure, eliminating the time required for multiple sequential patterning processes.
Solution Approach 2:
The patent performs preliminary pattern processing including polygon connection, evaluation feature placement, and guide contour generation before the lithography exposure. This preparatory work enables the single-exposure printing to achieve pattern fidelity equivalent to multiple patterning processes, significantly reducing production time.
3Ease of operation
If closely adjacent polygons are processed separately, then the processing simplicity is maintained, but the edge placement accuracy deteriorates
Solution Approach 1:
The patent merges closely adjacent polygons into connected components, treating them as unified structures rather than separate entities. The guide contour spans across these connected polygons, enabling the lithography system to maintain edge placement accuracy for sub-k1 features while keeping the processing approach relatively simple through automated pattern manipulation.
Solution Approach 2:
The patent introduces evaluation features and guide contours as intermediary elements between the original polygon data and the final lithography pattern. These intermediaries facilitate accurate edge placement by providing reference points and continuous contours that span across closely adjacent polygons, improving precision without significantly complicating the overall processing flow.
4Ease of manufacture
If a single patterning device pattern is used, then the manufacturing cost is reduced, but the patterning precision for sub-k1 features deteriorates
Solution Approach 1:
The patent merges closely adjacent polygons into connected components and uses guide contours spanning across these connections to enable single-pattern printing of sub-k1 features. This approach maintains patterning precision by treating multiple sub-k1 features as a unified pattern structure, allowing cost-effective single-exposure manufacturing without sacrificing the required precision for sub-k1 limit features.
Solution Approach 2:
The patent performs preliminary pattern processing to create connected components and generate guide contours before lithography. This preparation enables the single patterning device pattern to achieve sub-k1 printing precision by pre-organizing the pattern data structure, thereby reducing manufacturing cost while maintaining the required patterning precision.
Data Source
AI summary
A method for optimizing a patterning device pattern, the method including obtaining an initial design pattern having a plurality of polygons, causing at least some of the polygons to be effectively connected with each other, placing evaluation features outside the boundaries of the polygons, and creating a patterning device pattern spanning across the connected polygons based on the evaluation features.