Programmable Atomic Unit Memory Bounds Checking
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Solution Overview
Problem
Chiplet systems lack effective bounds checking for memory access, particularly in programmable atomic units (PAUs) without memory management units (MMUs), which can lead to data corruption and security breaches due to the absence of virtual memory features.
Innovation Solution
Implementing a programmable atomic unit (PAU) with a memory controller that calculates a contiguous memory address range based on a base memory address and interleave size, restricting access to ensure that only valid memory within the process's virtual address space is accessed, thereby mimicking MMU benefits without its complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a programmable atomic unit (PAU) without a memory management unit (MMU) is used in a chiplet system, then device complexity is reduced and ease of manufacture is improved, but memory access security deteriorates and data corruption risk increases due to lack of bounds checking
Solution Approach 1:
The patent introduces a memory controller as an intermediary component between the PAU and the memory system. The memory controller performs bounds checking on memory access requests generated by the PAU, calculating valid address ranges based on base addresses and interleave sizes. This mediator provides the necessary security checks without requiring a full MMU in the PAU, thus maintaining low complexity while improving reliability.
2Reliability
If virtual memory features are implemented in a PAU, then memory access security is improved, but device complexity increases and ease of manufacture deteriorates
Solution Approach 1:
The patent extracts the bounds checking functionality from the PAU and places it in the memory controller. The PAU generates memory access requests with base addresses, and the memory controller extracts and validates the address ranges by calculating contiguous memory address ranges based on interleave sizes. This separation allows security checks to be performed without embedding complex virtual memory features in the PAU itself.
3Reliability
If bounds checking is implemented in the memory controller for PAU memory requests, then memory access security is improved and data corruption is prevented, but processing time increases due to additional validation steps
Solution Approach 1:
The patent implements preliminary calculation of contiguous memory address ranges in the memory controller based on base addresses and interleave sizes. By pre-calculating valid address ranges and storing them in range registers, the bounds checking during actual memory access is simplified to a comparison operation. This preliminary action reduces the time penalty of bounds checking while maintaining data integrity.
Data Source
AI summary
Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.