Pausible Bisynchronous FIFO for Low-Latency Clock Domain Crossing
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Solution Overview
Problem
Modern system on a chip (SoC) designs face challenges with global timing closure due to slow wires and process, voltage, and temperature variations, making synchronous abstraction untenable, and the globally asynchronous, locally synchronous (GALS) design methodology difficult to implement effectively due to high latency and integration issues.
Innovation Solution
A pausible bisynchronous first-in first-out (FIFO) buffer system that uses a dual-port memory array for low-latency data transfer between clock domains, employing pausible clocking to minimize latency and energy consumption, and integrating well with standard CAD toolflows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional synchronous design is used across large chip areas, then timing closure becomes increasingly difficult to achieve, but partitioning into many small synchronous blocks (fine-grained GALS) introduces high latency at asynchronous boundaries and increases integration complexity
Solution Approach 1:
The patent divides the chip into multiple clock domains (synchronous islands) that can operate independently, allowing each segment to achieve timing closure locally without being constrained by global timing requirements across the entire chip
Solution Approach 2:
The patent introduces a specialized FIFO buffer structure that acts as an intermediary between different clock domains, enabling efficient data transfer with minimal latency while maintaining synchronization between domains
2Reliability
If fine-grained GALS design is implemented with many small synchronous blocks, then global timing closure is achieved, but the complexity of generating many local clocks and integrating into standard design toolflows increases
Solution Approach 1:
The patent presents a universal FIFO buffer design that can be applied across multiple clock domain interfaces, providing a standardized solution that simplifies integration into existing design toolflows while supporting fine-grained GALS architecture
Solution Approach 2:
The patent employs dynamic clocking mechanisms where clock signals can be selectively enabled or disabled based on data flow requirements, allowing the system to adapt to varying operational conditions and reduce unnecessary clock distribution complexity
3Ease of manufacture
If standard synchronous FIFO is used between clock domains, then data transfer is simple to implement, but latency increases due to asynchronous boundary crossing requirements
Solution Approach 1:
The patent uses preliminary synchronization mechanisms where pointer values are pre-synchronized between clock domains before data transfer, allowing the FIFO to operate with minimal latency while maintaining correctness across asynchronous boundaries
Solution Approach 2:
The patent employs dual-port memory with separate read and write pointers that can be independently controlled, allowing optimization of data transfer timing parameters to minimize latency while maintaining simple FIFO operation
Data Source
AI summary
A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is delayed and the increment signal to the second clock domain and is transmitted.