Pausing Column Readout in CMOS Image Sensors
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Solution Overview
Problem
Conventional CMOS image sensors face challenges in reducing sampling system noise and row-correlated visual artifacts due to overlapping sampling and readout operations, which increase susceptibility to noise during concurrent processing.
Innovation Solution
Implementing a method where the AFE clocking signal and column address sequence are suspended during sample operations, allowing for concurrent sample and read operations while storing pixel data to delay output and reduce noise, thereby reducing the time required to capture images and minimize noise in the captured images.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrent sampling and readout operations are implemented to reduce readout time, then productivity is improved, but sampling system noise increases causing row-correlated visual artifacts
Solution Approach 1:
The patent divides the concurrent sampling and readout operation into distinct time segments. During specific sampling intervals, the column address sequence is paused to prevent noise from being sampled. This segmentation allows the system to achieve both high frame readout rates through concurrency and low noise by separating sampling operations from active column addressing periods.
2Object-affected harmful factors
If clock signals are turned off during sampling to reduce noise, then sampling system noise is reduced, but readout operation cannot proceed concurrently
Solution Approach 1:
The patent dynamically controls the column address sequence based on the sampling phase. Instead of permanently disabling the clock signals, the system selectively pauses the column address sequence only during sampling intervals when noise reduction is critical, while maintaining concurrent readout operations during other periods. This dynamic approach allows the system to adapt between noise reduction and productivity requirements.
3Object-affected harmful factors
If the column address sequence is paused during sampling, then row-correlated visual artifacts are reduced, but the timing complexity of the readout operation increases
Solution Approach 1:
The patent implements preliminary control by pausing the column address sequence in advance during sampling operations before noise contamination can occur. The timing generator is designed to anticipate sampling phases and proactively suspend column addressing, ensuring that no noisy samples are taken during active column readout. This preliminary action simplifies the overall timing control by establishing clear, pre-determined pause points rather than requiring complex real-time coordination.
Data Source
AI summary
An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. An analog front end (AFE) circuit processes pixel data output from the output circuits and an AFE clock controller transmits an AFE clocking signal to the AFE circuit to effect processing of the pixel data. A timing generator outputs a column address sequence that is received by a column decoder. During one or more sample operations the timing generator suspends the column address sequence and subsequently during the one or more sample operations the AFE clock controller suspends the AFE clocking signal. The AFE clocking signal and the column address sequence resume at the end of the one or more sample operations.