Payload Cache Segmentation for CPU Interconnect Latency
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Solution Overview
Problem
Current computer systems face high average read latency and require high bandwidth interconnects due to the use of shared caches for payload and control data, which can lead to CPU performance degradation and complex interconnect design optimization, especially when CPU processes evict payload data from the shared cache to memory.
Innovation Solution
The system splits caching into payload data stored in a payload cache located near I/O interfaces and accelerators, and control data stored in a local CPU cache, eliminating the need for a shared cache and allowing separate management and optimization of each cache without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a shared cache is used for both payload data and control data, then cache utilization is improved, but average read latency increases and CPU performance degrades
Solution Approach 1:
The patent divides the shared cache into two separate physical caches: a payload cache for storing payload data and a local PU cache for storing control data. This segmentation allows each cache to be optimized for its specific data type, reducing read latency for both payload and control data while maintaining efficient cache utilization.
2Adaptability or versatility
If a shared cache is used for payload and control data, then memory resource sharing is improved, but interconnect bandwidth requirements increase
Solution Approach 1:
By segmenting the cache into separate payload cache and local PU cache, the patent reduces the bandwidth requirements of the interconnect between the processing unit and memory. Each cache can be accessed independently, eliminating the need for high-bandwidth interconnect to handle mixed payload and control data traffic.
3Adaptability or versatility
If CPU processes are allowed to access the shared cache, then cache versatility is improved, but payload data eviction occurs causing performance degradation
Solution Approach 1:
The patent creates a dedicated local PU cache for control data that is separate from the payload cache. This allows CPU processes to access control data without interfering with payload data storage. The payload cache remains dedicated to payload data, preventing eviction and maintaining high processing performance.
Solution Approach 2:
The patent implements different cache access policies for different data types. The local PU cache is optimized for control data access by CPU processes, while the payload cache is optimized for payload data storage with protection against eviction. Each cache has tailored access characteristics suited to its specific data type.
Data Source
AI summary
In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.