Unified PBCH and PDCCH Processing Chain for Shared L1 Blocks

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Solution Overview

Problem

Existing 5G New Radio (NR) systems separately implement Physical Broadcast Channel (PBCH) and Physical Downlink Control Channel (PDCCH) processing chains, leading to inefficiencies in resource utilization and processing time due to chain-specific customizations.

Innovation Solution

A unified common processing chain is developed to seamlessly process both PBCH and PDCCH Packet Data Units (PDUs) using a unified system with shared physical layer 1 (L1) sub-blocks, modifying control data through a cyclic redundancy check (CRC) engine, interleaving, rate matching, scrambling, and modulation based on control parameters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate processing chains are implemented for PBCH and PDCCH, then chain-specific customizations can be optimized, but resource utilization efficiency deteriorates and processing time increases

Engineering Contradiction:
Improvechain-specific customizationVSAvoidresource utilization efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges the previously separate PBCH and PDCCH processing chains into a unified common processing chain. The L1 sub-blocks (polar encoder, rate matcher, scrambler) are shared between both channels, eliminating redundant components while maintaining the ability to handle channel-specific requirements through parameter configuration rather than structural duplication.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The L1 sub-blocks in the unified processing chain are designed to be universal and multi-functional, capable of processing both PBCH and PDCCH data. The same polar encoder, rate matcher, and scrambler blocks can handle different channel types by receiving appropriate control parameters, thereby improving resource utilization without sacrificing channel-specific optimization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If separate processing chains are implemented for PBCH and PDCCH, then channel-specific requirements can be met, but processing time increases

Engineering Contradiction:
Improvechannel-specific requirement fulfillmentVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

By combining the processing chains, the patent eliminates the time required to transfer data between separate chains and reduces overall processing latency. The unified chain processes both PBCH and PDCCH through a single streamlined path, removing redundant processing steps while maintaining channel-specific functionality through parameter control.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If separate processing chains are implemented for PBCH and PDCCH, then independent optimization is possible, but device complexity increases

Engineering Contradiction:
Improveindependent optimization capabilityVSAvoidprocessing chain structure
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent employs universal L1 sub-blocks that can be independently optimized once and then reused for both PBCH and PDCCH processing. This multi-functional design reduces device complexity by eliminating duplicate components while preserving the ability to independently optimize each channel's performance characteristics through parameter configuration rather than structural modification.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250274220A1System and method for implementing a common processing chain for PBCH and pdcch channels
Publication Date: 2025.08.28 JIO PLATFORMS LTD
  • US20250274220A1 patent drawing
  • US20250274220A1 patent drawing
  • US20250274220A1 patent drawing

AI summary

The present disclosure relates to a system and a method for processing data in control channels. The system provides control data including a plurality of bits from the control channels to a cyclic redundancy check (CRC) block. The system determines if the plurality of bits corresponds to broadcast channel (BCH) data or downlink control information (DCI) data, and interleaves the plurality of bits if the plurality of bits corresponds to the BCH data, or bypasses interleaving of the plurality of bits if the plurality of bits corresponds to the DCI data. The system performs rate matching of the plurality of bits, and determines a length of a plurality of rate matched bits by setting an aggregation level for the control channels. The system performs scrambling operation on the plurality of rate matched bits, and modulates the plurality of rate matched bits based on scrambling operation outputs.