pBIST Engine with Distributed Data Logging for Memory Testing
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Solution Overview
Problem
Conventional high-speed memory testing in VLSI systems faces challenges such as inaccessible memory functions, limitations in CPU-based techniques, and inability to perform back-to-back accesses to all memories, leading to unobservable failures during testing.
Innovation Solution
A programmable built-in self-test (pBIST) system with a Distributed Data Logger (DDL) is employed, allowing asynchronous interfacing with multiple sub-chips for local data collection and failure detection, generating failure signatures, and communicating them to a controlling pBIST engine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CPU-based techniques are used for memory testing, then testing can be performed using existing processing resources, but the testing is limited by inaccessible memory functions and inability to perform back-to-back accesses
Solution Approach 1:
The system divides the testing architecture into separate components: a dedicated test engine independent of the CPU, distributed data loggers in each sub-chip, and separate test control logic. This segmentation allows the test engine to directly access memory functions without CPU intervention, enabling back-to-back accesses and accessing previously inaccessible memory areas.
Solution Approach 2:
A dedicated test engine acts as an intermediary between the testing system and memory, providing direct access to memory functions. The distributed data loggers serve as intermediaries for local data collection and comparison, enabling the test engine to perform comprehensive memory testing without relying on CPU-based techniques.
2Reliability
If a single centralized data logger is used, then system complexity is reduced, but testing coverage is limited and failures in multiple sub-chips cannot be detected locally
Solution Approach 1:
The centralized data logger is segmented into multiple distributed data loggers, with each logger located in a separate sub-chip. Each data logger independently collects test data, performs local comparisons, and detects failures in its associated memory units. This segmentation improves failure detection reliability while the modular design keeps individual logger complexity manageable.
Solution Approach 2:
Multiple distributed data loggers are merged into a coordinated system under the control of a single test engine. The loggers work together to provide comprehensive coverage across all sub-chips, combining their individual detection capabilities into a unified testing system that achieves high reliability without requiring a complex centralized architecture.
3Measurement precision
If external testing devices are used, then comprehensive memory testing can be performed, but the testing equipment becomes increasingly expensive and complex
Solution Approach 1:
The system implements built-in self-testing capabilities where the test engine and distributed data loggers are integrated directly into the device under test. The system tests itself using internal resources rather than requiring external testing equipment, achieving comprehensive memory testing accuracy while eliminating the need for expensive external testers.
Solution Approach 2:
The test engine is designed as a universal testing platform that can test multiple types of memory units across different sub-chips using the same hardware and software infrastructure. This multi-functionality provides comprehensive testing accuracy without requiring specialized expensive equipment for each memory type.
4Reliability
If conventional memory testing is performed during wafer form, then early defects can be detected, but direct memory accesses cannot be accomplished at full processor speed
Solution Approach 1:
The testing architecture is segmented to allow parallel operation of the test engine and data loggers, enabling full-speed memory accesses during testing. The distributed structure allows each component to operate independently at maximum speed while collectively achieving comprehensive defect detection.
Data Source
AI summary
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.