pBIST Pointer Register for ROM Testing Code Space Reduction
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Solution Overview
Problem
The increasing complexity of integrated circuits makes traditional testing methods difficult, and current built-in self-test (BIST) techniques, especially programmable BIST (pBIST), face challenges in supporting go/no-go testing and are inefficient in terms of code space and power usage, limiting their ability to effectively test read-only memory (ROM) and leading to the preference for using RAMs instead.
Innovation Solution
An integrated circuit with a built-in self-test unit that utilizes a test ROM storing sets of algorithms and data, featuring a programmable unit with new instructions that support data transpose operations, reducing code space and enabling efficient testing of operational circuits by using a pointer register to select normal or inverted data for comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional BIST techniques are used, then testing capability is provided, but code space consumption is excessive and power consumption is high
Solution Approach 1:
The patent combines test algorithms and test data into a unified test instruction structure stored in ROM. This merging eliminates the need for separate algorithm storage and data storage, significantly reducing code space while maintaining complete testing capability. The test engine executes instructions that contain both the algorithm logic and the test data together.
Solution Approach 2:
The patent creates a universal test instruction format that can perform multiple testing functions (write, read, compare, transpose operations) through a single instruction structure. This multi-functionality allows the same ROM-based test engine to handle various memory testing scenarios without requiring separate code for each function, thereby reducing overall code space consumption.
2Reliability
If traditional BIST techniques are used, then testing capability is provided, but power consumption is excessive
Solution Approach 1:
By merging test algorithms and test data into single test instructions stored in ROM, the patent reduces the number of memory access operations required. The test engine can execute complete test patterns from ROM without needing to load separate data sets, thereby reducing dynamic power consumption associated with memory accesses during test execution.
Solution Approach 2:
The patent prepares test instructions in advance by storing complete test algorithms and data combinations in ROM during manufacturing. This preliminary action eliminates the need to generate or load test data during operation, reducing runtime power consumption while maintaining full testing capability.
3Quantity of substance
If ROM-based testing is implemented, then code space is reduced, but support for go/no-go testing is lacking
Solution Approach 1:
The patent introduces dynamic control capabilities to the ROM-based test engine through programmable control logic. The test engine can dynamically adjust its operation mode based on control signals, enabling it to perform both exhaustive testing and go/no-go testing as needed. This dynamic adaptability allows the same hardware to support multiple testing strategies without requiring additional code space.
Solution Approach 2:
The patent enables go/no-go testing by changing the operational parameters of the test engine through control registers and configuration bits. By modifying parameters such as test termination conditions and result evaluation criteria, the system can switch between different testing modes including go/no-go testing, all while maintaining the compact ROM-based instruction structure.
Data Source
AI summary
This invention is new built-in self test instructions. A pointer register stores data identifying one bit of a data register. That bit determines whether the data of another data register is used in test in native form or in inverted form. Different built-in self test instructions update pointer including reset to the first bit, no change, increment to the next bit and decrement to the previous bit. For write instructions the selected normal or inverted data is written into memory. For read instructions the selected normal or inverted data is compared with data read from a memory.