pBIST ROM Organization for Embedded Memory Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional high-speed memory testing in VLSI systems faces challenges due to complex integrated circuit designs, limitations in CPU-based techniques, and the inability to perform back-to-back accesses to all memories, leading to unobservable failures during wafer-form memory testing.
Innovation Solution
A programmable Built-In Self Test (BIST) module with a novel ROM organization that reduces ROM requirements by storing memory testing and configuration information efficiently, allowing for shared data usage across similar embedded RAM instances, and utilizing a Distributed Data Logging system for localized comparison and reduced connection needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CPU-based memory testing techniques are used, then testing can be performed with existing hardware, but the inability to perform back-to-back accesses to all memories results in unobservable failures and reduced testing effectiveness
Solution Approach 1:
The patent implements a built-in self-test (BIST) system where the memory device tests itself using internal resources. The BIST controller generates test patterns and controls memory accesses independently of external CPUs, enabling back-to-back accesses to all memory locations without external intervention. This self-service approach resolves the contradiction by making the system autonomous for testing purposes, achieving both reliability improvement and operational capability.
Solution Approach 2:
The BIST controller is designed as a universal testing engine that can test multiple different memory types and configurations within the same device. It implements various memory access patterns and test algorithms that work across different memory instances, making the testing capability applicable to all memories in the device regardless of their specific characteristics. This universality enables comprehensive testing that CPU-based techniques cannot achieve.
2Reliability
If separate ROM storage is allocated for each embedded RAM instance, then each memory can be tested independently, but the total ROM size becomes excessively large
Solution Approach 1:
The patent merges the test pattern storage for multiple RAM instances into a single shared ROM structure. Instead of allocating separate ROM space for each memory instance, the BIST controller uses a unified address space that can selectively access and configure tests for different RAM instances. This consolidation reduces the total ROM size while maintaining the ability to independently test each memory through software-controlled address mapping.
Solution Approach 2:
The patent implements dynamic configuration of the BIST controller to adapt to different memory testing requirements. The controller can be programmatically configured through configuration registers to target specific RAM instances, adjust test parameters, and select appropriate test algorithms. This dynamic adaptability allows a single ROM to serve multiple memory instances with different characteristics, eliminating the need for static dedicated ROM allocation for each instance.
3Measurement precision
If extensive external testing devices are used to ensure comprehensive memory testing, then testing accuracy improves, but device complexity and cost increase
Solution Approach 1:
The memory device incorporates a complete self-testing capability that eliminates the need for complex external testing equipment. The BIST controller generates all necessary test patterns, controls memory accesses, and evaluates test results internally. This self-service approach achieves high measurement precision for defect detection while keeping the device complexity manageable by integrating testing functions within the existing device architecture rather than adding extensive external test systems.
Solution Approach 2:
The BIST controller acts as an intermediary between the memory arrays and any external testing interfaces. It translates high-level test requirements into specific memory access patterns and compares actual results against expected outcomes. This intermediary layer provides comprehensive defect detection accuracy while presenting a simple interface to external systems, effectively reducing the complexity of the overall testing system by absorbing the testing complexity within the device itself.
Data Source
AI summary
A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.