pBIST ROM Partitioning for Flexible Memory Testing
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Solution Overview
Problem
The increasing complexity of integrated circuits makes traditional testing methods difficult, and existing built-in self-test (BIST) techniques lack flexibility, especially in supporting go/no-go type testing and efficient data and algorithm management.
Innovation Solution
The proposed solution involves a programmable BIST unit that uniquely partitions the ROM for storing program and data information, allowing selective loading of algorithms and data, and includes configuration registers to control test execution, enabling flexible memory testing and efficient ROM-based testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional BIST techniques are used, then testing can be performed using built-in circuits, but flexibility in supporting go/no-go testing and efficient data/algorithm management is limited
Solution Approach 1:
The BIST unit is segmented into distinct functional components: algorithm storage region, data storage region, configuration registers, and test execution engine. This segmentation allows independent loading and management of algorithms and data, enhancing flexibility while maintaining manageable complexity through modular design.
Solution Approach 2:
The BIST unit implements dynamic configuration through writable configuration registers that allow runtime selection of test modes (including go/no-go testing) and selective loading of algorithms or data. This dynamic adaptability enables the system to reconfigure itself for different testing scenarios without hardware changes.
2Adaptability or versatility
If ROM-based testing is implemented, then test instructions can be stored on the integrated circuit, but ability to support go/no-go type testing is lacking
Solution Approach 1:
Test algorithms and data are pre-loaded into the ROM structure during manufacturing. The configuration registers are pre-configured with default values that enable go/no-go testing mode. This preliminary preparation allows the system to immediately support go/no-go testing without complex runtime configuration, maintaining operational simplicity.
Solution Approach 2:
Configuration registers serve as intermediaries between the ROM-based test instructions and the test execution engine. These registers translate high-level test type selections (including go/no-go modes) into specific operational parameters for the test engine, simplifying the interface while enabling sophisticated test types.
3Adaptability or versatility
If complete ROM-based testing is performed, then all test information is stored on-chip, but flexibility to download only specific information is reduced
Solution Approach 1:
The system extracts only the necessary portions of test information from the ROM based on configuration register settings. When go/no-go testing is selected, only the essential test algorithm is loaded and executed, while detailed data verification is omitted. This extraction approach reduces the effective storage and processing requirements while maintaining full ROM-based functionality.
Solution Approach 2:
The configuration registers enable parameter changes that control the depth and scope of test execution. By changing parameters in these registers, the system can switch between complete testing modes (loading all ROM content) and streamlined modes (loading only essential algorithms), effectively adjusting storage requirements based on testing needs.
Data Source
AI summary
This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each test set stored in the pBIST ROM into read/write registers. These registers are memory mapped readable/writable. A configuration register has an algorithm bit and a data bit which determines whether the corresponding algorithm or data is loaded from the pBIST ROM. The pBIST unit includes another configuration register having one bit corresponding to each possible test set stored in the pBIST ROM. The pBIST unit runs a test set if the corresponding bit in the configuration register has a first digital state.