DRAM Parallel Bit Test Region Segmentation for Fail Data Identification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DRAM memory systems face challenges in accurately identifying and correcting error bits during a parallel bit test (PBT), as the PBT mode fails to specify the exact memory cell causing the error, leading to undetected and uncorrected fail data, which can disrupt data center operations.
Innovation Solution
A memory device and system that divide memory cells into regions, perform a parallel bit test, select and output fail data including a fail data bit, and utilize an ECC engine to correct the fail data, ensuring accurate identification and correction of error bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a parallel bit test (PBT) is performed using XOR or XNOR logic circuits to reduce test time, then test efficiency is improved, but the ability to specify the exact fail memory cell is lost
Solution Approach 1:
The memory cell array is divided into multiple regions, and each region is tested separately using PBT. This segmentation allows the system to identify which specific region contains the fail data while maintaining the efficiency of parallel testing within each region.
Solution Approach 2:
A test controller is introduced as an intermediary component that coordinates the PBT operation across multiple regions and processes the test results. The test controller generates test commands, receives test data from each region, and determines which region contains the fail data based on the test results.
2Speed
If the same data is written to multiple memory cells for PBT comparison, then test speed is improved, but the ability to detect and correct specific error bits is compromised
Solution Approach 1:
The memory array is segmented into multiple regions that are tested in parallel. Each region undergoes PBT with the same data written to corresponding cells, maintaining test speed while enabling identification of which specific region contains errors through regional test result analysis.
Solution Approach 2:
The test controller receives test results from each region and uses this feedback to identify which region contains fail data. This feedback mechanism enables the system to pinpoint error locations while maintaining the speed benefits of parallel testing.
3Loss of time
If PBT is used to quickly test memory cells, then manufacturing time is reduced, but the precision of identifying failed bits deteriorates
Solution Approach 1:
The memory cell array is divided into multiple regions that can be tested simultaneously. This segmentation enables parallel testing across regions, significantly reducing total test time while maintaining the ability to identify which specific region contains fail bits.
Solution Approach 2:
The testing approach transitions from testing individual bits sequentially to testing entire regions in parallel by adding a spatial dimension (multiple regions tested simultaneously). This dimensional change reduces test time from linear to constant relative to the number of regions.
Data Source
AI summary
A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.