PC-Relative Load Instructions for Literal Data Delivery
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Solution Overview
Problem
Processor-based devices face challenges in generating large immediate values without using multiple instructions or larger instruction encodings, while avoiding the penalties associated with accessing literals via the data-access portion of the execution pipeline.
Innovation Solution
The use of program counter (PC)-relative load instructions to fetch literal data within the instruction processing portion of the execution pipeline circuit, allowing immediate values to be provided without incurring the overhead of data access pipeline penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If literal data is accessed via the data access portion of the execution pipeline, then the literal can be loaded from memory, but latency increases and resource hazards occur
Solution Approach 1:
The patent extracts the literal data access operation from the data access portion of the pipeline and moves it to the instruction processing portion. The literal data is fetched during the instruction fetch stage and made available to execution units earlier in the pipeline, eliminating the need to wait for data cache access in later stages.
Solution Approach 2:
The patent performs preliminary action by fetching and preparing literal data in advance during the instruction fetch stage, before the instruction that needs the literal is actually executed. This allows the literal to be ready when needed, avoiding latency during the critical execution path.
2Manufacturing precision
If multiple instructions are used to generate large immediate values, then the immediate value can be constructed, but code density decreases and multiple fetch/decode/execution lanes are required
Solution Approach 1:
The patent extends the immediate value field in the instruction format to accommodate 64-bit immediate values directly. By changing the dimension of the immediate field from 32-bit to 64-bit, the processor can load large immediate values in a single instruction without requiring multiple instructions or complex construction sequences.
3Manufacturing precision
If variable length instruction set is used to provide larger instruction encodings, then 64-bit immediate values can be communicated, but fetch complexity and decode complexity increase
Solution Approach 1:
The patent applies local quality by extending the immediate value field specifically in PC-relative load instructions where it is needed, rather than making all instructions variable length. This targeted approach maintains simplicity for the majority of instructions while providing the necessary capacity for large immediate values where required.
Data Source
AI summary
Delivering immediate values by using program counter (PC)-relative load instructions to fetch literal data in processor-based devices is disclosed. In this regard, a processing element (PE) of a processor-based device provides an execution pipeline circuit that comprises an instruction processing portion and a data access portion. Using a literal data access logic circuit, the PE detects a PC-relative load instruction within a fetch window that includes multiple fetched instructions. The PE determines that the PC-relative load instruction can be serviced using literal data that is available to the instruction processing portion of the execution pipeline circuit (e.g., located within the fetch window containing the PC-relative load instruction, or stored in a literal pool buffer), The PE then retrieves the literal data within the instruction processing portion of the execution pipeline circuit, and executes the PC-relative load instruction using the literal data.