Printed Wiring Board Adhesion via Surface Roughness Control
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Solution Overview
Problem
Existing printed wiring boards face challenges in preventing conductor layers from peeling off from resin insulating layers, particularly at via holes, due to differences in surface roughness and adhesion strengths between the conductor layers and the resin surfaces.
Innovation Solution
A printed wiring board design featuring a resin insulating layer with a via hole surface roughness greater than the boundary surface roughness, and a first surface roughness, where the via conductor connects the first and second conductor layers, ensuring the via conductor and second conductor layer adhere strongly to the resin insulating layer, suppressing peeling and maintaining signal propagation integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the surface roughness of the resin insulating layer is increased to improve adhesion, then the adhesion strength between conductor layers and resin increases, but the signal propagation integrity deteriorates due to noise and propagation speed differences
Solution Approach 1:
The patent applies different surface roughness characteristics to different regions of the resin insulating layer: the boundary part (where conductor layers contact) has higher surface roughness for enhanced adhesion, while the via hole inner wall has controlled roughness to balance adhesion and signal integrity. This localized differentiation resolves the contradiction by optimizing each region for its specific function.
Solution Approach 2:
The patent specifies precise surface roughness parameter ranges: the boundary part has arithmetic mean roughness Ra of 0.003 μm or more and 0.03 μm or less, while the via hole inner wall has Ra of 0.003 μm or more and 0.05 μm or less. By controlling these parameters within specific ranges, the patent achieves adequate adhesion while maintaining signal propagation integrity.
2Strength
If the surface roughness at the boundary part is increased to prevent peeling, then the adhesion between via conductor and resin improves, but the manufacturing precision deteriorates due to difficulty in controlling uniform roughness
Solution Approach 1:
The patent defines specific parameter ranges for surface roughness that are achievable through conventional manufacturing processes. The boundary part Ra of 0.003-0.03 μm and via hole inner wall Ra of 0.003-0.05 μm represent optimized ranges that balance adhesion requirements with manufacturing feasibility, resolving the contradiction between strength and precision.
Solution Approach 2:
The patent establishes surface roughness characteristics as a preliminary condition before conductor layer formation. By pre-defining the resin insulating layer's surface properties (boundary part and via hole inner wall roughness) before subsequent manufacturing steps, the patent ensures consistent adhesion while maintaining control over the manufacturing process.
3Stability of the object's composition
If the via hole inner wall surface roughness is increased to enhance via conductor adhesion, then the peeling resistance improves, but the signal noise increases due to irregular surface interactions
Solution Approach 1:
The patent differentiates surface roughness characteristics between the via hole inner wall and boundary part, with the via hole inner wall having controlled roughness (Ra: 0.003-0.05 μm) that provides adequate adhesion while minimizing signal noise compared to the higher roughness boundary part (Ra: 0.003-0.03 μm). This localized optimization resolves the contradiction between peeling resistance and signal quality.
Solution Approach 2:
The patent specifies a broader but still controlled roughness range for the via hole inner wall (Ra up to 0.05 μm) compared to the boundary part, allowing sufficient adhesion enhancement while maintaining signal integrity by preventing excessive roughness that would generate harmful noise.
Data Source
AI summary
A printed wiring board includes a first conductor layer, a resin insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the resin insulating layer, and a via conductor formed in the resin insulating layer such that the via conductor is connecting the first and second conductor layers and has a land portion extending on a boundary part of the resin insulating layer. The via conductor is formed in a via hole formed in the resin insulating layer. The resin insulating layer is formed such that the boundary part has a surface roughness that is larger than a surface roughness of the surface on which the second conductor layer formed and that an inner wall surface in the via hole in the resin insulating layer is equal to or larger than the surface roughness of the boundary part of the resin insulating layer.