Printed Wiring Board Asymmetric Copper Area Warping Control
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Solution Overview
Problem
Printed wiring boards experience warping during the reflow process due to uneven copper areas on the uppermost and lowermost conductive layers, leading to issues with IC chip mounting and connection reliability.
Innovation Solution
The design of printed wiring boards with a substrate having a first and second surface, featuring a first and second buildup layer with resin insulation and conductive layers, where the outermost conductive layers have specific area ratios between 1.1 to 1.35, ensuring controlled warping and improved mounting yields and connection reliability by adjusting the conductive layer areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the copper areas on the uppermost and lowermost conductive layers are made equal, then the warping of the printed wiring board is reduced, but the connection reliability and mounting yield deteriorate due to insufficient thermal stress control
Solution Approach 1:
The patent applies asymmetry by intentionally creating unequal copper areas between the uppermost and lowermost conductive layers. Specifically, the copper area of the lowermost conductive layer is made larger than that of the uppermost conductive layer, forming an asymmetric structure that generates controlled thermal stress during reflow processing. This asymmetric design prevents warping while maintaining connection reliability by balancing the thermal expansion forces.
Solution Approach 2:
The patent changes the parameter of copper area distribution between conductive layers. By adjusting the copper area ratio between the uppermost and lowermost layers to a specific range (0.5 to 0.85), the thermal stress characteristics are optimized. This parameter change enables simultaneous achievement of warping control and connection reliability during reflow processing.
2Stability of the object's composition
If the copper area of the lowermost conductive layer is increased relative to the uppermost, then warping is controlled through thermal stress balance, but the manufacturing complexity increases due to precise area ratio control requirements
Solution Approach 1:
The patent defines a specific parameter range for the copper area ratio (0.5 to 0.85) between uppermost and lowermost conductive layers. This quantitative parameter specification provides clear manufacturing guidelines, reducing the complexity of controlling the asymmetric structure while achieving the desired warping control effect.
3Stability of the object's composition
If dummy circuits are added to equalize copper areas, then warping is reduced, but the device complexity and manufacturing steps increase
Solution Approach 1:
Instead of adding dummy circuits to create symmetry, the patent employs asymmetry by intentionally designing unequal copper areas. This approach achieves warping control without increasing circuit complexity or adding unnecessary manufacturing steps, as the asymmetric copper distribution is integrated into the standard conductive layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The controlled warping of the component mounting region enhances IC chip mounting and connection reliability, reducing warping amounts to 20 μm to 70 μm, and ensures secure attachment and reduced thermal stress-induced failures.
Implementation Method 1
Printed wiring boards experience warping during the reflow process due to uneven copper areas on the uppermost and lowermost conductive layers
Data Source
AI summary
A printed wiring board includes a substrate, a first buildup formed on a first surface of the substrate and including the outermost conductive layer, and a second buildup layer formed on a second surface of the substrate and including the outermost conductive layer. The outermost layer of the first buildup has pads positioned to connect a semiconductor component, the first buildup has a component mounting region directly under the component such that the outermost layer of the first buildup has a portion in the region, the outermost layer of the second buildup has a portion directly under the region, and the portions satisfy the ratio in the range of from 1.1 to 1.35, where the ratio is obtained by dividing a planar area of the portion of the second buildup by a planar area of the portion of the first buildup.