PCB Package Ball Pitch Layout for LPDDR Routing Space

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Solution Overview

Problem

Existing methods for installing processing circuits on printed circuit boards (PCBs) face challenges in routing traces between vias due to equal ball pitches, leading to increased package area and costs when adapting to LPDDR standards like LPDDR5/5X.

Innovation Solution

Implementing a method with optimized pitch configurations for processing circuits on PCBs, where different pitch values are used in orthogonal directions to allow space for signal lines and vias, minimizing package area without significantly increasing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If equal ball pitch is used in both X and Y directions, then manufacturing is simplified, but routing traces between vias becomes difficult and package area increases

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidpackage area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent applies asymmetry by setting different ball pitches in the X-direction and Y-direction. Specifically, the ball pitch in the X-direction is set to 0.65mm while the ball pitch in the Y-direction is set to 0.8mm. This asymmetric configuration allows sufficient space for routing traces between vias in the X-direction while maintaining manufacturing simplicity, thereby resolving the contradiction between ease of manufacture and package area.

Inventive Principle:
Principle #4Asymmetry

2Adaptability or versatility

If ball pitch is increased to match memory package pitch, then compatibility with LPDDR standards is achieved, but package area greatly increases

Engineering Contradiction:
ImproveLPDDR standard compatibilityVSAvoidpackage area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by differentiating the ball pitch configuration in different directional regions. Instead of uniformly increasing the pitch in both directions to match LPDDR standards, the patent maintains 0.65mm pitch in the X-direction (where trace routing is critical) and increases to 0.8mm pitch only in the Y-direction. This localized differentiation achieves LPDDR standard compatibility while minimizing the overall package area increase.

Inventive Principle:
Principle #3Local quality

3Reliability

If many vias are arranged in SoC installation region, then connectivity is improved, but trace routing between vias becomes difficult with equal pitch

Engineering Contradiction:
ImproveconnectivityVSAvoidtrace routing ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies asymmetry by configuring different ball pitches in orthogonal directions to facilitate via arrangement and trace routing. With X-direction pitch of 0.65mm and Y-direction pitch of 0.8mm, the design allows vias to be arranged in a pattern that ensures adequate spacing for trace routing while maintaining high connectivity. The asymmetric pitch creates favorable geometric relationships for via placement and trace pathways.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20260020158A1Method of using optimized pitch for installing processing circuit at printed circuit board, and associated apparatus
Publication Date: 2026.01.15 REALTEK SEMICON CORP
  • US20260020158A1 patent drawing
  • US20260020158A1 patent drawing
  • US20260020158A1 patent drawing

AI summary

A method of using optimized pitch for installing a processing circuit at a printed circuit board (PCB) and associated apparatus are provided. The method may include: providing a set of first terminals on a predetermined surface of a package of the processing circuit, the set of first terminals corresponding to a set of first pads within a first sub-region of a predetermined installation region of the PCB, where a first pitch of the set of first terminals along a predetermined direction is equal to a first predetermined value; and providing a set of second terminals on the predetermined surface of the package of the processing circuit, the set of second terminals corresponding to a set of second pads within a second sub-region of the predetermined installation region, where a second pitch of the set of second terminals along the predetermined direction is equal to a second predetermined value.