PCB Bump Pad Structure to Prevent Solder Bridging and Cracking
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Solution Overview
Problem
The reduction in pitch of bump pads on printed circuit boards leads to issues such as solder bridges and cracking during chip mounting, especially in high-density semiconductor chip installations, causing serious defects.
Innovation Solution
A printed circuit board design with layered substrate and wiring patterns, including conductive via layers, an outermost insulating layer, and bump pads with controlled lengths and protruding solder dams, along with solder resist layers to prevent short circuits and cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of bump pads is reduced to increase integration density, then the number of chips that can be mounted per area increases, but solder bridges occur causing short circuits
Solution Approach 1:
The bump pad structure is segmented into multiple functional zones: a wider upper portion for solder placement and a narrower lower portion for electrical connection. This segmentation allows the solder to be contained within the upper portion while the narrower lower portion prevents solder bridges between adjacent bump pads, thus enabling high integration density without short circuits.
Solution Approach 2:
Different portions of the bump pad have different dimensions tailored to specific functions. The upper portion has a larger area to receive and contain the solder, while the lower portion has a smaller area for electrical connection. This local quality differentiation ensures that solder is confined to appropriate areas, preventing short circuits while maintaining high density.
2Productivity
If the pitch of bump pads is reduced to increase integration density, then more chips can be mounted per area, but cracking occurs in the bump pad during soldering
Solution Approach 1:
The bump pad is divided into an upper portion and a lower portion with different cross-sectional areas. The upper portion has larger dimensions that provide structural support and stress distribution during soldering, while the lower portion maintains electrical connection. This segmentation allows the bump pad to withstand soldering stresses without cracking while maintaining small pitch for high density.
Solution Approach 2:
The bump pad exhibits local quality variation where the upper portion has enhanced mechanical strength through larger dimensions to resist cracking during soldering, while the lower portion maintains smaller dimensions for electrical function. This localized strength enhancement prevents bump pad failure during the soldering process.
3Productivity
If the pitch of bump pads is reduced to increase integration density, then chip capacity increases, but solder wicking to the node causes serious defects
Solution Approach 1:
The bump pad structure is segmented with the upper portion positioned at a higher elevation than the surrounding insulating layer and other structures. This segmentation creates a physical barrier that prevents solder from wicking down to the node during the soldering process, eliminating the harmful effect of solder wicking while maintaining high integration density.
Solution Approach 2:
The bump pad upper portion is designed to protrude in the vertical dimension above the insulating layer and other planar structures. This dimensional elevation creates a solder dam effect that contains solder within the bump pad upper portion, preventing lateral and vertical wicking to adjacent nodes, thus preventing solder-related defects while enabling high density.
Data Source
AI summary
A printed circuit board includes: a substrate layer in which a plurality of insulating layers and a plurality of wiring patterns are repeatedly layered, the substrate layer including a conductive via layer disposed in one of the plurality of insulating layers to connect wiring patterns, among the plurality of wiring patterns, disposed on upper and lower surfaces of the one insulating layer, respectively; an uppermost substrate layer including an outermost insulating layer disposed outermost within the substrate layer, and a first upper wiring pattern disposed in the outermost insulating layer; and a bump pad disposed on a portion of an upper surface of the first upper wiring pattern and having a length shorter than a length of the first upper wiring pattern.