PCB Buried Traces via Laser Ablation and Plating
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Solution Overview
Problem
As semiconductor specifications increase, the size of dies grows, leading to higher production costs. To mitigate this, there is a need for efficient interconnection techniques between dies that minimize signal loss under high-frequency conditions and allow for impedance management and design flexibility.
Innovation Solution
The proposed solution involves forming printed circuit boards with buried trace structures. This is achieved by creating concave portions in insulating layers using laser processing, forming via holes of varying depths and widths, and filling these features with conductor patterns through a plating process followed by planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional wiring methods are used, then manufacturing is simpler, but surface roughness increases causing signal loss under high frequency conditions
Solution Approach 1:
Instead of forming conductor patterns by etching (removing material), this patent uses a deposition method where conductor material is filled into concave portions formed by laser processing. This inversion of the conventional approach eliminates the surface roughness problem inherent in etching-based methods while maintaining manufacturing feasibility.
Solution Approach 2:
The patent replaces mechanical etching processes with laser-based concave portion formation followed by electroless plating deposition. This substitution of mechanical removal with optical heating and chemical deposition achieves smoother conductor surfaces that reduce high-frequency signal loss.
2Adaptability or versatility
If via holes with uniform dimensions are used, then manufacturing is easier, but design flexibility and impedance management are limited
Solution Approach 1:
The patent applies different via hole dimensions at different locations and depths within the multilayer structure. By forming concave portions with varying depths and filling them with plating to create via holes of different sizes, the design achieves local optimization for impedance management and signal integrity without requiring complete redesign of the entire via system.
Solution Approach 2:
The via hole structure is made dynamically adjustable by controlling the depth of concave portions formed by laser processing and the amount of plating material deposited. This allows via dimensions to be optimized for specific signal requirements rather than being fixed by conventional uniform via designs.
3Productivity
If fine lines and spaces are implemented, then circuit density increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent forms concave portions with precise dimensions using laser processing before filling them with conductor material through plating. This preliminary formation of the cavity structure allows for precise control of final conductor dimensions, enabling fine lines and spaces to be manufactured with the required precision by defining the geometry before material deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the realization of fine lines/spaces and vias, reduces surface roughness to minimize signal loss under high-frequency conditions, facilitates impedance management through adjustable circuit pattern thickness, and enhances design freedom and signal integrity.
Implementation Method 1
forming concave portions having various depths and widths in each insulating layer using laser processing
Implementation Method 2
forming a conductor pattern layer and a via pattern by performing a planarization process fill after filling the concave portions and via holes with plating
Data Source
AI summary
The present disclosure relates to a printed circuit board. The printed circuit board includes a plurality of insulating layers each having a plurality of concave portions; a plurality of conductor pattern layers disposed in a plurality of concave portions of each of the plurality of insulating layers; first and second via holes connected to one of the plurality of concave portions independently of each other and penetrating through at least two of the plurality of insulating layers independently of each other; and first and second via conductors disposed in the first and second via holes, respectively, and connecting two of the plurality of conductor pattern layers independently of each other. An average width of the first via conductor is greater than that of the second via conductor on a cross-section.