PCB Capacitor Array via Alternating Layer Placement
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Solution Overview
Problem
In computing systems, capacitive coupling between vias on printed circuit boards (PCBs) leads to signal noise and performance errors, necessitating increased spacing that consumes valuable PCB area, balancing area usage and coupling reduction.
Innovation Solution
The implementation of an alternating pattern of AC coupling/DC blocking capacitors on both sides of the PCB, combined with back-drilling of vias to minimize stub lengths and the introduction of a ground plane to isolate capacitors, allowing for a dense array that reduces capacitive coupling while conserving board space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If vias are spaced apart to reduce capacitive coupling, then capacitive coupling between vias is reduced, but PCB area is consumed
Solution Approach 1:
The patent utilizes the third dimension by placing blocking capacitors on different layers of the PCB (top layer and internal layers) rather than only on the same plane. This vertical stacking allows vias to be spaced closer together horizontally while maintaining reduced capacitive coupling through the layered capacitor arrangement, effectively transitioning from 2D spacing to 3D spatial management.
Solution Approach 2:
Blocking capacitors are introduced as intermediary elements between adjacent vias. These capacitors act as mediators that actively cancel out the capacitive coupling between vias through differential signaling. The capacitors are positioned to form coupled pairs that create equal and opposite capacitive effects, thereby neutralizing the harmful coupling without requiring large physical spacing between vias.
2Area of stationary object
If blocking capacitors are placed close together to save space, then PCB area is saved, but capacitive coupling increases
Solution Approach 1:
The patent resolves this contradiction by moving the capacitive coupling mitigation from the horizontal plane to the vertical dimension. Blocking capacitors are placed on different PCB layers (e.g., top layer and second internal layer) directly above or below each other. This vertical arrangement allows horizontal spacing to be minimized for space efficiency while the layered structure provides electromagnetic isolation that reduces capacitive coupling between adjacent vias.
Solution Approach 2:
The blocking capacitors themselves serve as intermediaries that, when properly paired and positioned across different layers, create a differential effect that cancels capacitive coupling. The capacitive coupling between a via and its associated blocking capacitor on one layer is counterbalanced by the coupling to the paired capacitor on another layer, effectively neutralizing the harmful effect while allowing close spacing.
3Ease of manufacture
If conventional capacitor placement is used, then manufacturing is simple, but capacitive coupling reduction is minimal
Solution Approach 1:
The patent extends conventional two-dimensional capacitor placement into the third dimension by utilizing multiple PCB layers. Blocking capacitors are strategically positioned on different layers (top layer, internal layers) to create vertical stacking arrangements. This approach maintains manufacturing simplicity through standard multi-layer PCB fabrication processes while achieving superior capacitive coupling reduction through the added dimensional complexity.
Solution Approach 2:
The patent employs blocking capacitors as intermediary elements that actively participate in signal coupling mitigation. These capacitors are positioned to form differential pairs where one capacitor blocks capacitive coupling in one direction while its paired capacitor on another layer blocks coupling in the opposite direction, creating a balanced system that reduces overall capacitive interference while maintaining ease of manufacture through standard capacitor components and placement techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement significantly decreases capacitive coupling between vias, enabling a more compact PCB design with reduced signal interference, thus enhancing computing system performance without sacrificing area efficiency.
Implementation Method 1
AC coupling/DC blocking capacitors
Data Source
AI summary
Implementations of the present disclosure involve an apparatus and/or method for a large array of AC coupling/DC blocking capacitors on a printed circuit board (PCB) of a microelectronic circuit. The method provides for the placement of the blocking capacitors (and associated vias) to be placed on/through the PCB in a small area while yielding low crosstalk or interference between the vias. In one particular embodiment, the blocking capacitors are placed on the PCB in an alternating pattern, with a pair of blocking capacitors placed on the top side of the PCB followed by a pair of blocking capacitors on the bottom side of the PCB, and so on. Further, top side capacitor vias may be back-drilled from the bottom side and bottom side capacitor vias may be back-drilled from the top side.