PCB Capacitor Network for Power Supply Noise Reduction

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Solution Overview

Problem

Conventional printed circuit boards with a single capacitor struggle to cope with the increasing operating frequencies of semiconductor chips, leading to undesirable inductance effects and power supply noise due to varying current consumption.

Innovation Solution

A printed circuit board design featuring multiple capacitors with alternating grounding and power supply wiring patterns, connected in parallel, to reduce inductance components and accommodate various frequency characteristics of semiconductor chips, thereby mitigating power supply noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single capacitor is used in the printed circuit board, then the device complexity is reduced, but the ability to cope with various frequency characteristics and reduce inductance effects deteriorates

Engineering Contradiction:
Improvecapacitor configurationVSAvoidfrequency characteristic adaptation
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The single capacitor is segmented into multiple capacitors with different capacitance values (e.g., 0.1μF and 0.01μF). Each capacitor handles different frequency ranges, with the larger capacitor addressing lower frequencies and the smaller capacitor addressing higher frequencies. This segmentation resolves the contradiction by maintaining simplicity through modular components while achieving versatility across the frequency spectrum.

Inventive Principle:
Principle #1Segmentation

2Speed

If the operating frequency of the semiconductor chip is increased, then the processing speed and performance are improved, but the inductance effects and power supply noise become more pronounced

Engineering Contradiction:
Improveoperating frequencyVSAvoidinductance effects
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The invention changes the electrical parameters of the capacitor network by using multiple capacitors with different capacitance values instead of a single capacitor. This parameter change allows the system to maintain low inductance effects across a broader frequency range, enabling higher operating frequencies without the harmful inductance effects that would otherwise limit performance.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If a single capacitor with fixed capacitance is used, then the manufacturing process is simplified, but the ability to reduce power supply noise across various frequency ranges deteriorates

Engineering Contradiction:
Improvecapacitor installationVSAvoidpower supply noise
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The power supply noise reduction function is segmented across multiple capacitors with different capacitance values, where each capacitor targets specific frequency ranges. This segmentation maintains ease of manufacture through standardized capacitor components while effectively reducing power supply noise across the entire frequency spectrum through the combined action of multiple capacitors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention applies parameter changes by selecting capacitors with different capacitance values (e.g., 0.1μF and 0.01μF) to address different frequency ranges of power supply noise. This parameter variation allows the system to maintain simple manufacturing procedures while achieving comprehensive noise reduction that a single fixed-capacitance capacitor cannot provide.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8179689B2Printed circuit board, method of fabricating printed circuit board, and semiconductor device
Publication Date: 2012.05.15 SHINKO ELECTRIC IND CO LTD
  • US8179689B2 patent drawing
  • US8179689B2 patent drawing
  • US8179689B2 patent drawing

AI summary

A printed circuit board has capacitors, a grounding wiring pattern having a bonding surface on which a semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to first electrodes of the capacitors, and a power supply wiring pattern having a bonding surface on which the semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to second electrodes of the capacitors. The grounding and power supply wiring patterns are alternately arranged in a predetermined direction, and the capacitors are coupled in parallel with respect to the grounding and power supply wiring patterns.