Multilayer PCB Embedded Capacitor Thickness Control

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Solution Overview

Problem

The existing multi-layer printed wiring boards with embedded capacitors face challenges in maintaining constant electrostatic capacity due to variations in dielectric layer thickness and difficulty in connecting internal conductive layers to external layers, particularly in seven-layer structures.

Innovation Solution

A five-layer structure is proposed with a middle conductive layer sandwiched by two dielectric layers, where the dielectric layers are formed directly on the conductive layers without intermediate layers, ensuring uniform thickness and integration through pressing, and using thermosetting resin with dielectric particles to enhance electrostatic capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dielectric layer is formed on a conductive layer with a circuit pattern, then a capacitor structure can be created, but the thickness of the dielectric layer becomes difficult to make constant

Engineering Contradiction:
Improveelectrostatic capacity consistencyVSAvoiddielectric layer thickness uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The invention forms the dielectric layer on a flat conductive layer surface before any circuit pattern formation. This preliminary action ensures that the dielectric layer is deposited on a uniform, flat surface, making it possible to achieve constant thickness across the entire layer. The circuit patterns are then formed on top of this uniformly thick dielectric layer, eliminating the manufacturing difficulty of achieving thickness uniformity when forming dielectric layers on patterned surfaces.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a seven-layer structure is used for the capacitive stack, then the capacitor can be embedded in the printed wiring board, but connecting the internal conductive layers to external layers becomes difficult

Engineering Contradiction:
Improveembedded capacitor integrationVSAvoidconductive layer connection complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention divides the capacitive stack into separate functional layers with clear interfaces. The dielectric layer is segmented to extend beyond the circuit patterns, creating distinct regions for capacitor formation and circuit routing. This segmentation simplifies the connection of internal conductive layers to external layers by providing clear access points and reducing the complexity of the seven-layer structure.

Inventive Principle:
Principle #1Segmentation

3Reliability

If the dielectric layer thickness varies, then the electrostatic capacity of the capacitor varies, but maintaining constant thickness is difficult when forming on patterned surfaces

Engineering Contradiction:
Improveelectrostatic capacity stabilityVSAvoiddielectric layer formation difficulty
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The dielectric layer is formed in advance on a flat conductive layer surface before any circuit patterning is performed. This preliminary formation on a flat surface ensures uniform thickness and consistent electrostatic capacity. The circuit patterns are then created on top of this uniform dielectric layer, making the manufacturing process easier while maintaining capacitor reliability.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively suppresses electrostatic capacity variations and facilitates easy connection of internal and external conductive layers, improving the reliability and performance of embedded capacitors in multi-layer printed wiring boards.

Implementation Method 1

a first dielectric layer 12a is provided on a first surface of the middle conductive layer 11a, and a second dielectric layer 12b is provided on a second surface of the middle conductive layer 11a

Methodology Applied
Scientific EffectElectrostatic field: Electric Field

Implementation Method 2

using thermosetting resin with dielectric particles to enhance electrostatic capacity

Methodology Applied
Scientific EffectDielectric permittivity: Dielectric Permittivity

Data Source

PatentUS11285700B2Multilayer laminate and method for producing multilayer printed wiring board using same
Publication Date: 2022.03.29 MITSUI MINING & SMELTING CO LTD
  • US11285700B2 patent drawing
  • US11285700B2 patent drawing
  • US11285700B2 patent drawing

AI summary

A multi-layered board includes: a middle conductive layer; a first dielectric layer that is disposed directly on a first surface of the middle conductive layer; a second dielectric layer that is disposed directly on a second surface of the middle conductive layer; a first outer surface conductive layer that is disposed directly on an outer side of the first dielectric layer; and a second outer surface conductive layer that is disposed directly on an outer side of the second dielectric layer. The first outer surface conductive layer serves as a first outer surface of the multi-layered board, and the second outer surface conductive layer serves as a second outer surface of the multi-layered board. The middle conductive layer is solidly formed over an entire planar direction of the multi-layered board. The first dielectric layer and the second dielectric layer each independently have a thickness variation of 15% or less.