PCB Cavity Layout for Embedded Passive Device Parallel Connection
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Solution Overview
Problem
In printed circuit boards for semiconductor packages, surface-mounted land side capacitors limit the number of solder balls and increase the distance between the semiconductor chip and the capacitor, while embedded passive structures face challenges in matching device thickness and connecting passive devices in parallel.
Innovation Solution
The printed circuit board design includes first and second cavities passing through insulating layers, allowing for the embedding of passive devices, which minimizes the distance between the semiconductor chip and the passive devices and facilitates easy parallel connection of multiple passive devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LSC is mounted on the surface of the board, then power integrity characteristic is secured, but the number of solder balls is limited and the distance between semiconductor chip and LSC increases
Solution Approach 1:
The patent transitions from surface mounting (2D plane) to embedded mounting (3D volume) by creating cavities within the insulating layers. This dimensional change allows passive devices to be positioned closer to the semiconductor chip in the vertical direction, reducing the distance while maintaining power integrity characteristics.
Solution Approach 2:
The passive devices are nested within cavities formed in the insulating layers of the printed circuit board. This nesting approach allows the passive devices to be embedded inside the board structure rather than mounted on the surface, enabling closer proximity to the semiconductor chip and increasing the number of available solder balls.
2Reliability
If EPS structure is used, then passive devices are embedded in the board, but there are difficulties in matching thickness of passive device and CCL and connecting passive devices in parallel
Solution Approach 1:
The patent modifies the cavity dimensions and positions to accommodate passive devices with varying thicknesses. By adjusting cavity parameters (size, depth, location) rather than requiring precise passive device thickness matching, the design simplifies the integration process while maintaining reliable embedded connections.
Solution Approach 2:
The board structure is segmented into multiple insulating layers with cavities formed at different positions and orientations. This segmentation allows passive devices to be connected in parallel through separate cavity paths, reducing the complexity of parallel connections compared to traditional EPS structures.
Data Source
AI summary
A printed circuit board includes: a first board unit including a plurality of first insulating layers and a plurality of first wiring layers respectively disposed on or in the plurality of first insulating layers; a second board unit including one or more second insulating layers and one or more second wiring layers respectively disposed on or in the one or more second insulating layers; and a first passive device embedded in at least one of the first and second board units. The second board unit is disposed on the first board unit, and the first board unit has a second cavity passing through at least a portion of the plurality of first insulating layers on the first passive device based on a stacking direction of the plurality of first wiring layers.