PCB Cooling Surface Layout for Void-Reduced Chip Soldering
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Solution Overview
Problem
The existing reflow soldering process for chip packages on printed circuit boards often results in defects such as trapped flux gases forming bubbles in solder joints, reducing heat transfer efficiency due to insufficient flux escape and tolerances in contact pads leading to gaps between heat dissipation and cooling surfaces.
Innovation Solution
A printed circuit board design with a metallic cooling surface, surrounding contact surfaces, and a rear metallic counter surface connected by open vias, along with solder resist lanes dividing the cooling surface into partial areas, allows gaseous flux to escape through vias and excess solder to flow off, ensuring a reliable thermal connection by compensating for volume loss and tolerances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder paste is dispensed onto contact surfaces and heated to melt the solder, then the solder bonds the chip housing to the circuit board, but gaseous flux becomes trapped in the solidifying solder and forms bubbles that impair heat transfer
Solution Approach 1:
The cooling surface is divided into multiple partial surfaces by lanes of solder resist, creating segmented areas that facilitate controlled flux gas escape paths while maintaining effective thermal contact areas
Solution Approach 2:
Open vias are provided that extract and remove gaseous flux from the solder joint area during the soldering process, allowing bubbles to escape through the vias rather than becoming trapped in the solidifying solder
2Temperature
If the cooling surface is made as large as possible to ensure good heat transfer, then thermal connection is improved, but the gap between cooling surface and heat dissipation surface becomes too large to bridge with solder due to tolerance variations
Solution Approach 1:
Solder paste is dispensed in excess onto the partial surfaces and contact surfaces, ensuring that even with tolerance variations and gaps, there is sufficient solder material to bridge the gap and create reliable thermal and electrical connections
Solution Approach 2:
The cooling surface is segmented into partial surfaces separated by solder resist lanes, allowing the solder to be distributed across multiple smaller contact areas that can better accommodate tolerance variations while maintaining overall thermal connection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a low void percentage in solder joints, enhancing heat transfer efficiency and ensuring consistent, reproducible soldering results by effectively managing flux escape and filling gaps between heat dissipation and cooling surfaces.
Implementation Method 1
the solder paste melts into solder at the soldering temperature
Implementation Method 2
the solder outgasses through the vias
Implementation Method 3
excess solder flows off through the vias onto the mating surface, connects with the mating surface and runs on the mating surface
Implementation Method 4
in a cooling step the solder solidifies on the contact surfaces and contact feet, between the heat dissipation surface and the partial surfaces
Implementation Method 5
ensuring a reliable thermal connection by compensating for volume loss and tolerances
Data Source
AI summary
The present disclosure relates to a method for the process-reliable soldering of a chip package onto a printed circuit board for the process-reliable soldering of a chip package. The printed circuit board has a metallic cooling surface, a plurality of metallic contact surfaces surrounding the cooling surface, and, on a side opposite the cooling surface, a rear metallic mating surface, the mating surface being connected to the cooling surface by open vias, and lanes of solder resist being arranged on the cooling surface, which lanes both divide the cooling surface into a plurality of partial surfaces and enclose the vias.