PCB Core Layer Property Identification via Plated Via Conductance
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Solution Overview
Problem
Tracking manufacturing properties of printed circuit boards (PCBs) with multiple layers is challenging due to changes in raw material sources and manufacturing processes over time, making it difficult to diagnose defects and predict potential failures, especially since internal core layers become inaccessible after lamination.
Innovation Solution
Incorporating a metal core code on the inner core layer that can be measured through plated vias, allowing for the identification of manufacturing properties by measuring electrical conductance between reference and test vias, which corresponds to a core lot code that tracks the properties of each core layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional PCB manufacturing processes are used with multiple layers, then production efficiency and manufacturing capability are improved, but tracking and identifying core layer properties becomes difficult after lamination
Solution Approach 1:
The patent applies preliminary action by embedding core codes and test structures into the PCB core layers during the manufacturing process, before lamination occurs. This allows the core layer properties to be encoded and stored within the structure itself, enabling later identification without requiring external records or documentation that might be lost or inaccessible.
Solution Approach 2:
The patent uses an intermediary approach by introducing core codes as a mediating element between the core layer and the identification process. These core codes serve as a bridge that carries property information through the lamination process and enables non-destructive testing later, without interfering with the normal PCB structure or function.
2Loss of information
If core layer properties are tracked through external records, then information can be stored, but costly record-keeping systems and potential errors are required
Solution Approach 1:
The patent applies self-service by enabling the PCB structure itself to store and provide access to its own manufacturing property information through the core codes. The PCB becomes self-documented, eliminating the need for separate external record-keeping systems. The core layer properties are encoded directly into the PCB structure, allowing the PCB to 'tell' its own manufacturing history through non-destructive electrical measurements.
3Measurement precision
If x-ray watermark methods are used to track core layer properties, then identification capability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent replaces the mechanical/x-ray based identification system with an electrical measurement system. Instead of using x-ray watermarks that require complex imaging equipment and processing, the invention uses electrical conductance measurements through plated vias to read the core codes. This substitution simplifies the manufacturing process and reduces equipment complexity while maintaining identification precision.
Solution Approach 2:
The patent changes the measurement parameter from optical/x-ray properties to electrical conductance properties. By encoding core layer information in electrical conductance patterns that can be measured through plated vias, the invention enables simpler manufacturing and testing processes compared to x-ray watermark methods, while achieving the same goal of core layer identification.
4Measurement precision
If internal core layers are made accessible for testing, then property identification is improved, but destructive means are currently required
Solution Approach 1:
The patent uses plated vias as intermediaries to access the embedded core codes in internal core layers without destructive means. These vias serve as conductive pathways that allow electrical measurements to reach the core layer properties encoded within the PCB structure, enabling non-destructive testing while maintaining the integrity of the multi-layer construction.
Solution Approach 2:
The patent replaces destructive mechanical access methods with non-destructive electrical measurement methods. Instead of physically sectioning or disassembling the PCB to access core layers, the invention uses electrical conductance measurements through plated vias to read core layer properties, thereby preserving the PCB structure and enabling post-manufacturing identification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the precise tracking and identification of manufacturing properties of each core layer after lamination, facilitating defect diagnosis and reducing the need for costly record-keeping and x-ray watermark methods, thereby improving PCB reliability and reducing the risk of product malfunctions.
Implementation Method 1
measuring an electrical conductance between the reference via and the test via
Data Source
AI summary
A reference via in a set of plated vias on a printed circuit board is located. A reference lead is applied to the reference via. A test via in the set of plated vias is located. A test lead is applied to the test via. An electrical conductance between the reference via and the test via is measured. A property of a core layer of the printed circuit board is identified based on the electrical conductance.