PCB Core Layer CTE Mismatch Warpage Prevention
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Solution Overview
Problem
Semiconductor packages are prone to warpage due to coefficient of thermal expansion (CTE) mismatch between semiconductor chips, molding resin, and printed circuit boards (PCBs) during manufacturing processes, leading to bonding failures when stacked or mounted on motherboards.
Innovation Solution
A printed circuit board (PCB) with a core layer having a stacked structure of materials with different CTEs, an upper wiring layer, and a lower wiring layer is used, where the core layer consists of at least two sub-layers with distinct CTEs, and the upper and lower wiring layers are disposed accordingly to mitigate warpage by balancing thermal expansion differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-material core layer is used in the PCB, then the structure is simple and easy to manufacture, but the semiconductor package experiences warpage due to CTE mismatch during thermal processes
Solution Approach 1:
The core layer is constructed as a composite structure with a first sub-core layer (lower CTE) and a second sub-core layer (higher CTE). This composite configuration allows the PCB to balance thermal expansion forces during manufacturing processes, preventing warpage and ensuring reliable bonding of the semiconductor package while maintaining manufacturability.
Solution Approach 2:
The invention changes the CTE parameter distribution within the core layer by using multiple sub-layers with different CTE values. The first sub-core layer has a lower CTE and the second sub-core layer has a higher CTE, creating a balanced thermal expansion profile that prevents warpage during thermal processes without complicating the manufacturing process.
2Reliability
If materials with different CTEs are stacked in the core layer, then warpage is prevented through balanced thermal expansion, but the device structure becomes more complex
Solution Approach 1:
The core layer uses a composite structure of two sub-core layers with different CTE values. The first sub-core layer (lower CTE) and second sub-core layer (higher CTE) are stacked to create balanced thermal expansion characteristics, preventing warpage while maintaining a relatively simple overall device structure.
Solution Approach 2:
Different regions of the core layer (first and second sub-core layers) have different CTE properties tailored to specific functional needs. The first sub-core layer provides lower CTE for stability, while the second sub-core layer provides higher CTE for compensation, creating local quality variations that prevent warpage without requiring complex overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents warpage of semiconductor packages by balancing thermal expansion forces, ensuring stable bonding and mounting of semiconductor chips, thereby reducing the risk of failures during stacking and mounting on motherboards.
Implementation Method 1
a core layer having a stacked structure including at least a first layer made of a first material that has a first coefficient of thermal expansion (CTE) and a second layer made of a second material that has a second CTE different from the first CTE
Data Source
AI summary
Provided are a printed circuit board (PCB) and a semiconductor package including the same. The PCB includes a core layer having a stacked structure including at least a first layer made of a first material that has a first coefficient of thermal expansion (CTE) and a second layer made of a second material that has a second CTE different from the first CTE, an upper wiring layer disposed on a first surface of the core layer, and a lower wiring layer disposed on a second surface of the core layer opposite the first surface.