PCB Debugging via Boundary-Scan Circuit Graph Visualization
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Solution Overview
Problem
Debugging modern printed circuit boards with multiple layers is challenging due to invisible conductive tracks and small components, making it difficult to distinguish and test individual pins and connections, which can lead to malfunctioning boards.
Innovation Solution
A method using an electronic processing unit to retrieve and display boundary-scan properties and connectivity data, generating a circuit graph for visualization through a graphical user interface, allowing users to select components and interconnects for debugging, enabling efficient testing and fault identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If boundary-scan testing is implemented on multi-layer PCBs, then testing coverage of internal tracks is improved, but debugging complexity increases due to invisible conductive tracks and small components
Solution Approach 1:
The patent creates a visual copy or representation of the physical PCB circuit layout, allowing debuggers to see a graphical map of conductive tracks and components. This virtual representation mirrors the actual board structure, enabling visualization of invisible internal tracks through software-generated diagrams rather than physical inspection.
Solution Approach 2:
The patent introduces an intermediary software system that acts as a mediator between the boundary-scan test data and the debugger. This intermediary processes test results, correlates them with the circuit layout database, and presents simplified visual information, reducing the complexity of direct debugging while maintaining comprehensive test coverage.
2Reliability
If all components and tracks are monitored to ensure correct functioning, then board reliability is improved, but testing time and resource requirements increase
Solution Approach 1:
The patent performs preliminary actions by pre-loading and storing the complete circuit layout information, component locations, and track routing data into a database before testing begins. This preliminary preparation allows the testing system to quickly reference and correlate test results with specific circuit elements during actual debugging, reducing testing time while maintaining comprehensive monitoring capability.
Solution Approach 2:
The patent implements partial monitoring by allowing the debugger to focus on specific regions, components, or track segments rather than requiring simultaneous analysis of the entire PCB. The system enables selective visualization and testing of particular circuit areas, reducing overall testing time while still ensuring reliability of monitored portions.
Data Source
AI summary
A method of debugging a printed circuit board with at least one boundary-scan compliant device is presented. The method uses an electronic processing unit and includes the steps of: retrieving boundary-scan properties of the at least one boundary-scan compliant device, the properties including a listing of boundary-scan compliant circuit terminals of the at least one boundary-scan compliant device; retrieving connectivity properties; selecting and displaying a circuit graph of at least a part of the devices mounted on the printed circuit board, the circuit graph including at least one of the devices mounted on the printed circuit board and a least one further device from the devices which has a circuit terminal interconnected to a circuit terminal of the device for visualizing at least the device, the further device and interconnects between the circuit terminals of the devices.