PCB Edge Launch Transition Reducing Parasitic Inductance
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Solution Overview
Problem
Establishing high-quality microwave/mmW connections beyond 20 GHz is challenging due to parasitic inductance issues at the transition from planar to coaxial transmission lines on printed circuit boards, with existing solutions either limited in frequency capability or requiring manual trimming that can degrade performance.
Innovation Solution
An edge launch transition is fabricated using conventional printed circuit board techniques, featuring an elongated edge-plated region and an edge launch extending outwardly to provide a well-defined RF ground path, which reduces parasitic inductance and tolerates mounting irregularities and angular misalignment without post-manufacturing trimming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ground vias are added at the edge of the printed circuit board to improve planar to coaxial transition, then the connection quality is improved, but parasitic inductance increases due to the inherent inductance of the ground vias
Solution Approach 1:
The patent transitions from using vertical ground vias to an edge-launch configuration where the ground connection extends along the edge of the PCB in a planar dimension. This dimensional change allows the ground path to be formed by edge plating that wraps around the PCB edge, creating a distributed ground path that reduces inductance compared to discrete via connections.
Solution Approach 2:
The patent introduces an intermediate ground path formed by edge plating that connects the ground planes on opposite sides of the PCB. This intermediate structure serves as a low-inductance mediator between the ground planes, avoiding the need for high-inductance via connections while maintaining electrical continuity.
2Reliability
If wrap-around plating is added on the edge of the board to improve frequency capability, then the frequency capability is improved, but manual post-fabrication trimming is required which may remove dielectric material and degrade performance
Solution Approach 1:
The patent incorporates the edge-launch ground structure directly into the PCB fabrication process through edge plating applied before final assembly. The ground path is pre-formed by plating the edge of the PCB and routing it to connect ground planes, eliminating the need for post-fabrication trimming or manual adjustments.
Solution Approach 2:
The edge-launch configuration is designed to be self-aligning and self-adjusting. The ground path automatically compensates for minor manufacturing variations and assembly misalignments, eliminating the need for manual trimming or post-fabrication adjustments that could remove critical dielectric material.
3Object-generated harmful factors
If elongated side of via holes is edge-plated to reduce parasitic inductance, then the parasitic inductance is reduced, but the routing diameter must be substantially greater than drilled round vias which prevents placing conductor close to the microstrip launch area
Solution Approach 1:
The patent moves the ground connection from a vertical via-based approach to a horizontal edge-launch approach along the PCB edge. This allows the ground path to extend laterally close to the microstrip launch area without requiring deep or elongated vias, achieving low inductance while maintaining compact geometry.
Solution Approach 2:
The patent uses an asymmetric edge-launch configuration where the ground path is formed by plating that wraps around the PCB edge in an irregular pattern. This asymmetric routing allows the ground conductor to be positioned optimally close to the microstrip launch area, achieving better performance than symmetric via-based approaches.
Data Source
AI summary
An edge launch and fabrication method wherein spaced elongated slots are formed through a circuit board. The slots are plated at least along one side thereof connecting ground planes of the circuit board thus forming spaced edge plated regions. Circuit modules are produced by singulating the circuit board along a cut line offset outwardly from the plated slot sides to form an edge launch outwardly extending from and between the spaced edge plated regions.