PCB Embedded Spaces Reduce Warpage via CTE Mismatch Mitigation
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Solution Overview
Problem
Printed circuit boards (PCBs) experience warpage due to mismatched coefficients of thermal expansion (CTE) between the board and mounted components, leading to assembly issues and reliability concerns.
Innovation Solution
Incorporating embedded spaces on the PCBs to mount components closer to the center, reducing the volume and height of the board underneath the components, thereby mitigating CTE mismatch and warpage, and allowing for the use of components with lower CTE values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If components are mounted on the outer surface of the PCB, then the assembly process is simple, but warpage occurs due to CTE mismatch between the board and components
Solution Approach 1:
The patent embeds components within recesses formed in the PCB substrate, nesting the component inside the board structure rather than mounting it on the surface. This nesting approach reduces the distance between the component and the neutral axis of the PCB, thereby reducing warpage caused by CTE mismatch while maintaining assembly feasibility through automated placement processes
Solution Approach 2:
The patent transitions from two-dimensional surface mounting to three-dimensional embedding by creating recesses within the PCB substrate. This dimensional change allows components to be positioned at different depths, optimizing their location relative to the neutral axis to minimize warpage while preserving electrical connectivity through vias and traces
2Stability of the object's composition
If components are embedded closer to the center of the PCB, then warpage is reduced, but the board volume and height increase
Solution Approach 1:
The patent creates localized recesses only in the specific regions where components need to be embedded, rather than increasing the overall board volume uniformly. This local modification approach minimizes the impact on total board volume and height while achieving the warpage reduction benefit of center-proximity component placement
3Shape
If components are mounted on the outer surface, then the board profile remains compact, but solder joint reliability deteriorates due to warpage
Solution Approach 1:
By nesting components within recesses in the PCB substrate, the patent maintains a compact overall board profile while positioning components closer to the neutral axis. This dual benefit preserves the compact shape while significantly improving solder joint reliability by reducing warpage-induced stress on the joints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces warpage and improves the reliability of solder joints and overall profile of the PCB assembly by minimizing thermal expansion mismatches, enhancing the assembly process and component integration.
Implementation Method 1
mismatched coefficients of thermal expansion (CTE) between the board and mounted components
Data Source
AI summary
Various embodiments described herein provide for printed circuit boards with one or more spaces for embedding components, which can be used to implement a memory sub-system.