Printed Wiring Board Equipotential Cavity Design
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Solution Overview
Problem
Existing printed wiring boards face issues with interlayer short circuits between conductor layers, particularly when electronic components are integrated, leading to potential damage and performance degradation.
Innovation Solution
A printed wiring board design featuring a core substrate with through-hole conductors connecting front and back conductor layers, and build-up layers with interlayer insulating and conductor layers, where conductor layers sandwiching interlayer insulating layers maintain the same electric potential in regions surrounding cavities for electronic components, preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conductor layers are placed close to each other to reduce board thickness, then productivity and compactness improve, but interlayer short circuits occur between conductor layers
Solution Approach 1:
The patent applies equipotentiality by making adjacent conductor layers have the same electric potential through connection via via holes. Specifically, conductor layers on both the front and back surfaces are connected to a common potential through conductive vias, ensuring that even when layers are closely spaced, no potential difference exists between them, thereby preventing short circuits while allowing reduced board thickness
Solution Approach 2:
The patent uses via holes filled with conductive material as intermediaries to connect conductor layers across insulating layers. These via conductors act as mediators that equalize potential between adjacent conductor layers, enabling close spacing without short circuits by providing a controlled potential equalization path between layers
2Length of moving object
If insulating layers are made thinner to reduce overall board thickness, then compactness improves, but the risk of interlayer short circuits increases
Solution Approach 1:
By establishing equipotential conditions between adjacent conductor layers through via connections, the patent eliminates the need for thick insulating layers solely for electrical isolation. The insulating layers can be thinner because the potential equalization via via holes prevents breakdown, allowing reduced insulating layer thickness without compromising short circuit resistance
Solution Approach 2:
The patent transitions from relying solely on the thickness dimension of insulating layers for isolation to using the vertical via connection dimension for potential equalization. This dimensional shift allows thinner insulating layers by providing an alternative mechanism (via-based potential equalization) to prevent short circuits, moving the solution from a 2D planar isolation approach to a 3D volumetric approach
Data Source
AI summary
A printed wiring board includes a core substrate having cavity to accommodate an electronic component and including a front conductor layer formed on front side of the core substrate, and a back conductor layer formed on back side of the core substrate, through-hole conductors formed through the core substrate such that the through-hole conductors connect the front and back conductor layers of the core substrate, a front build-up layer formed on front surface of the core substrate and including interlayer insulating layers and conductor layers, and a back build-up layer formed on back surface of the core substrate and including interlayer insulating layers and conductor layers. The conductor layers in the front build-up layer include a conductor layer sandwiching one of the interlayer insulating layers with the front conductor layer such that the conductor layer and the front conductor layer have the same electric potential in region surrounding the cavity.